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Functional ECOs provide a critical late-stage optimization step for any design. This is where errors are corrected, optimization is applied, and late-stage customer requests are accommodated. Since this process occurs late in the design cycle, there is significant risk regarding the introduction of an error that will escape to silicon, creating a very costly and time-consuming problem.

Functional ECO automation can dramatically reduce the chances of an error escape. The specific benefits include:

• Efficiency. The ECO is implemented with the minimum amount of re-work.
• Time-to-market. Since these changes occur near tapeout, delays can translate into a late to market problem if not handled well.
• Confidence. Intelligent logic equivalence checking (LEC) ensures the changes have not modified the behavior of the chip in an unintended way.

Since functional ECOs are typically applied to the design late in the process, there is less opportunity to verify and optimize these changes. Essentially, the changes need to be ¡°right from the start¡±. Some challenges to overcome include:

• Efficiency of the patch. An inefficient process will add a lot new logic to the netlist, which can cause routing congestion and timing issues.
• Optimized synthesis. If the re-targeted RTL isn¡¯t focused properly in the key areas requiring re-synthesis, the process will take too long and time-to-market can be impacted.
• Robust verification. Logic equivalency checking (LEC) is typically applied to the original design and the patched design to verify there are no unintended consequences of the ECO. Some ECOs can perform optimizations that make LEC difficult (e.g., datapath optimization).