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Accelerate Design Closure
草榴社区' design analysis and signoff solution includes a broad portfolio of products for static timing analysis, advanced signal integrity, power and power integrity, parasitic extraction, ECO closure, transistor-level analysis and library characterization. The native integration of signoff technologies with IC Compiler? II and Fusion Compiler allows physical designers to confidently realize the full performance-power-area (PPA) potential of the design with the fastest path to design closure.
Key Benefits
Resources
Solution Overview
Timing and ECO Closure
草榴社区’ PrimeTime? solution delivers fast, memory-efficient scalar and multicore static timing analysis, distributed multi-scenario analysis and ECO fixing using POCV and variation-aware modeling.
草榴社区 PrimeClosure is the industry’s first AI-driven golden signoff ECO closure solution and is??integrated with industry-golden 草榴社区 PrimeTime Static Timing Analysis and 草榴社区 Fusion Compiler? RTL-to-GDSII implementation solution to accelerate electronic-design power-performance-area closure time-to-results (TTR).
草榴社区 PrimeShield solution provides the industry’s fastest design robustness analysis solution built on golden PrimeTimeSTA and accelerated with breakthrough machine learning technology.?
Transistor-level Signoff
草榴社区 NanoTime is the golden timing signoff solution for transistor-level design for CPU datapaths, embedded memories and complex AMS IP blocks.?
Its seamless integration with 草榴社区’ PrimeTime? product enables full-chip analysis of designs that includes both gate- and transistor-level blocks. 草榴社区 NanoTime is a key component of the 草榴社区 custom design verification solution that includes 草榴社区 CustomSim? and HSPICE for circuit simulation and 草榴社区 ESP for symbolic simulation-based equivalence checking.
Power and Power-Integrity Closure
草榴社区 PrimePower analyzes power dissipation for block and full-chip designs starting from RTL, through implementation, and leading to power signoff.
RedHawk Analysis Fusion provides early, comprehensive in-design power integrity analysis and fixing in 草榴社区 IC Compiler?II and 草榴社区 Fusion Compiler? solutions, enabling signoff accuracy during physical design implementation.?
Library Characterization
The 草榴社区 SiliconSmart? solution provides fast, accurate, and advanced node proven library characterization for standard cells, I/O and memory.? 草榴社区 PrimeLib is the next-generation, unified library characterization and validation solution, providing ultra-fast, signoff-quality libraries and is optimized for scaling and performance for cloud and cluster computing workloads.
草榴社区 SiliconSmart and 草榴社区 PrimeLib innovative technologies utilize embedded gold-reference SPICE engines to provide a characterization speed-up of advanced Liberty models used by 草榴社区 PrimeTime static timing analysis to accurately account for effects seen in ultra-low-voltage FinFET processes that impact timing.
Parasitic Modeling and Extraction
The 草榴社区 StarRC? solution provides golden signoff parasitic extraction for silicon accurate results?supporting advanced foundry nodes and design flows.?
The 草榴社区 QuickCap? NX solution is the golden?extraction reference tool?for advanced node?process?modeling and high accuracy library characterization.
