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We are very excited to  of our high-performance hardware-assisted verification (HAV) portfolio: ²ÝÁñÉçÇø HAPS-200 and ZeBu-200.

Based on the latest AMD Versal Premium VP1902 adaptive system-on-chip (SoC), both solutions deliver faster runtime performance, better compile times, and enhanced debug productivity compared to their trend-setting predecessors, HAPS-100 and ZeBu EP.

ZeBu-200 augments ZeBu Server 5 ¡ª the industry¡¯s highest-capacity and best-density emulation system ¡ª with higher performance emulation for design capacities up to 15.4 billion gates (BGs). This gives developers more flexibility to choose between performance, capacity, and density.

Developers will also experience accelerated software bring-up (like Android boot in mobile applications) with hybrid emulation now supporting the new, faster multi-threading technology of our Virtualizer Virtual Prototyping.

Finally, we are working with customers to conquer verification challenges for advanced designs beyond 60 BG by extending our Modular HAV methodology from HAPS prototyping to ZeBu emulation.

Figure 1: The industry¡¯s highest performance hardware-assisted verification portfolio.

What¡¯s driving these expansions?

Compounding complexities ¡ª spanning software, hardware, interfaces, and workload-optimized architectures ¡ª are creating tremendous challenges for those developing today¡¯s most advanced chip, system on chip (SoC), and multi-die designs. Verification and software development processes, in particular, can require quadrillions of test and validation cycles across simulation, emulation, and prototyping stages. As a result, there has been a distinct need for faster HAV solutions that accelerate the development and validation of advanced chip designs and help ensure optimized functionality of the software-defined systems they enable.

Figure 2: Compounding complexities are driving hardware-assisted verification requirements.

EP-Ready Hardware delivers unmatched ROI and flexibility

HAPS-200 and ZeBu-200 are built on our EP-Ready Hardware, which can be reconfigured (through software and cabling) for all emulation and prototyping use cases ¡ª from detailed RTL verification to high-speed software validation. In addition to delivering unmatched ROI, this flexibility directly addresses one of the most challenging aspects of verification planning.

Design teams have traditionally been forced to make hardware decisions and investments based on early predictions of verification requirements. As a result, they often encounter resource shortages (requiring additional projections and investments) or underutilization (wasted budget) as projects and requirements evolve.

Our EP-Ready Hardware platform eliminates this guesswork and associated investments, significantly improving:

• Resource optimization. Teams can support all verification use cases (and manage multiple projects simultaneously) with a single hardware platform rather than maintaining different heterogeneous hardware pools for emulation and prototyping.
• Risk mitigation. The ability to reconfigure hardware reduces the risks associated with early verification planning decisions. As project needs shift, teams can adjust their verification approach without additional hardware investments.
• Operational efficiency. Managing a single hardware platform for both emulation and prototyping systems can reduce operational complexity, training, and maintenance.

Figure 3: ²ÝÁñÉçÇø EP-Ready Hardware platform with two software stacks for emulation and prototyping systems.

Modular HAV methodology expands capacity and reduces the time and cost of software bring-up

Modern chip architectures are inherently modular, with multiple chiplets connected through standards like UCIe and protocols like AXI and CHI. As growing hardware and software complexity leads to disaggregation of chiplets, verification methodologies are disaggregating as well.

Figure 4: ²ÝÁñÉçÇø Modular HAV methodology.