Cloud native EDA tools & pre-optimized hardware platforms
STING is a bare metal functional verification tool designed to serve as a platform for the design verification of RISC-V-based CPU and SoC implementations. It applies industry best practices and methodologies while providing solutions for the unique challenges of specific processor ecosystems.
The STING software stack consists of test generators, checkers, device drivers, and a lightweight kernel which can be configured into a portable program for the needs of the verification environment. The program can seamlessly boot on simulation, FPGA prototypes, emulation, or silicon and execute the constrained random, directed, or coverage-based tests that the user has specified. The highly portable stimulus is controlled by a rich file-based user input specification scheme. High levels of control are provided for every test parameter, so that every condition can be mapped to a particular test configuration.
Adopted and deployed by multiple RISC-V CPU and system vendors, STING has been used to successfully verify hundreds of system designs of varying complexity.
Stress the design in areas such as message passing, memory coherence and consistency
Tailored to match the speed of the platform and achieve horizontal test reuse from simulation silicon
A UI designed to make complex test specification easy
A single source of test stimulus that can be used in simulation, emulation, FPGA prototypes, and silicon
A combination of approaches to generate interesting stimulus
Custom extensions can be added for proprietary IPs
Features to facilitate debug of failing tests:
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