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End-to-End Solution for Enabling Energy-Efficient System-on-Chips
Energy-efficient System-on-Chips (SoCs) have become a critical need in all major markets from battery-operated devices for mobile, wearables, IoT, aerospace, and automotive applications to wired applications for high-performance compute (HPC), artificial intelligence (AI), data centers, networking, and storage. Energy consumption of the chip, which affects battery-life, form-factor, cooling and heat-dissipation costs, power-performance tradeoffs, and ultimately the carbon footprint and fuel consumption of the end-products, drives many key design and business decisions. To achieve optimal energy efficiency, low power techniques must encompass every facet of the chip design and verification from silicon to software. 草榴社区 delivers an end-to-end solution for energy-efficient SoCs across design, verification and IP products.
Key Benefits
Achieve Optimal PPA, Faster
Design energy-efficient SoCs with 草榴社区 solutions for software-driven low power design
Detect Low Power Bugs Early
Find low power bugs earlier and reduce re-spins with a comprehensive low power verification solution
Accelerate Time-to-Market
Leverage a broad portfolio of low power IP solutions to get your SoCs to market faster
Explore Our Solution
Design
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Designing Energy-Efficient SoCs
草榴社区 offers software-driven, low power exploration, analysis and optimization from architecture to signoff. At the early stages of design, 草榴社区’ virtual-prototyping solutions enable system architects to explore and tune the macro-architecture and embedded software for low power. Software workloads can then be profiled in the power emulator to identify key windows of interest for downstream power analysis and optimization. A comprehensive solution for RTL power exploration and analysis can be used to further tune the micro-architecture for low power. Automatic power-optimization techniques in the RTL-to-GDSII implementation flow ensure that design meets power-performance-area (PPA) targets followed by high-accuracy power signoff. The entire flow supports UPF (IEEE 1801) low power intent.
Verify
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Verifying Energy-Efficient SoCs
草榴社区 offers a comprehensive low power verification solution based on UPF (IEEE 1801) power?intent. This includes verification of the UPF low power intent and exhaustive functional verification of?the design in the presence of low power techniques expressed in UPF. The solution spans static?verification for low power checks, UPF-aware formal verification, low power simulation, early SoC architecture analysis, and optimization for power, emulation and?prototyping. Integrated with the verification solution is a unified low power debug, planning and?coverage solution to ensure that designers can effectively root-cause low power bugs?and also ensure?the design meets its functional coverage goals.
Maximize
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Maximizing Energy Efficiency
With semiconductor IP, designers can incorporate the most advanced functionalities in their complex SoCs for a wide range of applications including mobile, automotive, and high-performance computing (HPC). SoCs for battery-operated devices and high-end compute systems require IP that offers maximum energy efficiency while maintaining high performance. 草榴社区’ DesignWare? Interface, Foundation and Processor IP portfolio supports a wide-range of power features and is designed with the latest advanced low power techniques, including multi-voltage design, power-gating, configurability, and more.
Videos
草榴社区 Solution for RTL to Signoff Power Analysis
Piyush Sancheti, Vice President System Architects Group, explains how to perform full-chip power analysis with predicable accuracy from early RTL stage all the way to implementation and signoff.
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