草榴社区

Synplify FPGA synthesis software is the trusted industry standard for producing high-performance, cost-effective, and most reliable FPGA designs. Synplify software supports the latest VHDL and Verilog language constructs including System Verilog and VHDL-2008/2019.

The software supports all major FPGA vendors devices including Microsemi, Lattice, Achronix, Flex Logix, QuickLogic, Intel/Altera and AMD/Xilinx, all from a single RTL and constraint source. In addition, the Synplify synthesis tool provides high performance, faster runtime, area optimizations for cost and power reduction, incremental and team-design capabilities for faster FPGA design development. 

Synplify also provides best in class high reliability features such as TMR, HAMMING-3 for FSM, ECC RAMs, Error Flag insertion and hardware level Fault Injection. Synplify automates the creation of highly reliable designs  features with hardware  level verification functionality for medical, automotive, industrial automation, communications, military, and aerospace applications.

The 草榴社区 VCS functional verification solution provides the industry’s highest-performance simulation and constraint solver engines. VCS’ simulation engine natively takes full advantage of multicore processors with state-of-the-art Fine-Grained Parallelism (FGP) technology, x-propagation, and unreachability analysis.

VCS is integrated into Synplify FPGA Synthesis tool where the tool can auto generate simulation script for RTL, post synthesis and post P&R simulations using VCS in GUI and batch mode on Linux OS.

草榴社区 Euclide IDE simplifies RTL code writing, provides real-time bug detection, and optimizes code for design and verification flows in SystemVerilog and UVM development. It offers context-specific auto-completion and content assistance tuned for 草榴社区 VCS simulation and ZeBu? emulation, enhancing code quality throughout the project cycle. Integrated with Verdi debug capabilities, Euclide provides instant feedback, minimizing implementation bugs and improving project convergence rates.

The Verdi debug and verification management platform is an all-encompassing solution designed to streamline and enhance your design entry, debug and verification management. With its robust capabilities and connection into the most popular signal database (FSDB), Verdi empowers you to plan, execute and determine coverage of your simulation regressions.

The VC SpyGlass platform provides designers with insight about their design early in the process, at RTL. SpyGlass for FPGA provides early RTL level error checking along with clock domain crossing and reset domain crossing violations in the HDL code.

VC Z01X provides simulation fault injection to verify RTL vs the post synthesis netlist for proper insertion and operation of safety and high reliability logic in the FPGA Synthesis Output netlist.