草榴社区 SLM Process, Voltage & Temperature Monitor IP
Process, Voltage and Temperature (PVT) monitoring is critical to achieve reliable operation and optimum performance of advanced node (FinFET, Gate-All-Around (GAA)) semiconductor devices. Increasing transistor density, multi-die ICs and pushing silicon performance boundaries is making monitoring of PVT parameters throughout the silicon lifecycle a necessity. Based on the output of these monitors actions can be taken to optimize silicon health.
The 草榴社区 SLM PVT IP portfolio includes process detector, voltage monitor, glitch detector, temperature sensor, distributed temperature sensor, catastrophic temperature sensor and thermal diode.
Figure 1: PVT Controller with PVT Monitor IP?
Unique Modular Solution
Belonging to the Silicon Lifecycle Management (SLM) family, the PVT Monitor IP from 草榴社区 offers a high accuracy, highly featured and modular solution which can be tailored to the customer’s requirements. The well-supported monitoring solution for SoC designs is available from 28nm down to 3nm in both commercial and automotive grades.
For GAA process nodes, the monitors will leverage digitally assisted analog (DAA) architecture providing smaller size and ease of integration.
PVT Controller and Driver
The PVT Controller is highly configurable and manages the subsystem of monitors, relieving the system control processor of many tasks associated with PVT monitoring. For a large die, multiple instances of the PVT Controller, each with its own subsystem of PVT monitors, can be instantiated.
A reference bare metal software driver is now also included with the PVT Controller Series 5 that is ISA (Instruction Set Architecture) agnostic and portable.
Figure 2: Reference bare metal software driver
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草榴社区 In-Chip PVT Monitoring and Sensing
Real-Time Analysis such as:
- Real-time, highly granular thermal mapping across the die
- IR drop analysis
- Continuous energy and power optimization (DVFS, AVS support)
Silicon Assessment & Health Monitoring such as:
- Provides real-time adaptive adjustments of test limits versus the traditional DPAT approach, improving quality as measured by DPPM as well as yield
- Correlation of monitor data with existing parametric test data providing real-time accurate, adaptive adjustment of the upper and lower limits on a per die basis
- Process spread measurement during test phase
- Per-chip optimization for power and speed performance
- Age monitoring of silicon during device lifecycle
- Predictive reliability for extended SoC lifetime