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Verification IP for Memory
草榴社区 Verification IP (VIP) for memory leverages the same proven, 100% native SystemVerilog UVM architecture as 草榴社区 interface and bus VIP. It offers the same advantages for ease of use, ease of integration and performance and includes verification plans, built-in coverage and support of the Verdi? Protocol Analyzer protocol-aware memory debug environment. Memory VIP is a complete verification IP solution that accelerates verification closure for designers of memory controllers and SoCs.
Memory VIP can be configured on-the-fly by part number or attribute to rapidly verify interfaces against a range of components without the need to recompile. The DDR memory VIP also includes built-in support for DIMM, RDIMM and LRDIMM configurations: A single instantiation of the memory can be configured on-the-fly as any DIMM, removing the need to instantiate multiple components and implement buffering.
Through our close collaboration with 草榴社区 to develop the next-generation memory technologies, we enable mutual customers to successfully adopt the latest memory solutions."
Jinman Han
|Senior Vice President, Samsung
Memory Model Certification
草榴社区 provides a comprehensive set of DRAM and Flash Memory VIP that support the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI. 草榴社区’ VIP team works closely with leading memory vendors to certify 100% compatibility with their manufactured parts. 草榴社区 Memory VIP is used by memory controller and PHY IP design teams for verification sign off using run time and random JEDEC, vendor part selection, protocol, timing checks, and functional coverage. The early adoption and collaboration with leading memory vendors, SoC market makers, and industry leading IP teams certify the quality of 草榴社区 Memory VIP.
