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²ÝÁñÉçÇø Verification IP (VIP) for Ethernet 10/100/1000M and up to 1.6T provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of Ethernet based designs.

VIP, based on its next-generation architecture and implemented in native SystemVerilog and UVM, runs natively on all major simulators. VIP can be integrated, configured and customized with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.