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Dr. Daniel Bliss never imagined he would become a chip designer.
The Arizona State University (ASU) professor, physicist, and self-described problem solver has a background in systems engineering, not silicon.
And yet, with his long-term research on the cusp of major breakthroughs, he couldn’t find chips that were flexible or efficient enough for the next-gen systems he was seeking to enable.
“We’ve been developing communication systems, radar systems, navigation systems, even some biomedical stuff,” says Dr. Bliss, noting much of his team’s work is performed in collaboration with other universities and supported by U.S. Department of Defense Advanced Research Projects Agency () grant funding. “All of the interesting things we want to do are computationally expensive.”
With commercially available semiconductors proving too costly, rigid, or inefficient for the systems he and his team wanted to develop, Dr. Bliss set out to create his own specialized chips.
“I felt like I had no other choice,” he says.
Figure 1: Dr. Daniel Bliss, ASU professor and researcher, with the 草榴社区 HAPS-100.
From concept to creation: The long haul of chip development
Dr. Bliss and his team at ASU’s Center for Wireless Systems and Computational Architectures () set out to develop a new type of chip architecture. One that doesn’t force trade-offs between processing flexibility and power efficiency. One that integrates advanced accelerators with dynamic, intelligent drivers and sophisticated runtime software. One that has the potential to revolutionize a host of communications systems — from the phones in our pockets to the satellites in low Earth orbit.
Their work attracted the attention of DARPA, received grant funding for multiple projects (including and ), and even spawned a commercial venture ().
But the chips still had to be pushed from concept to creation.
“It’s a long haul and a lot of work,” Dr. Bliss says of the semiconductor development process. “It’s easy to get overly focused on hardware design, but the hardware only matters if you’re doing something useful with it. So, software ends up being half the system.”
When the system is a complex, multi-engine System-on-Chip (SoC) that contains two billion transistors and is designed for ad hoc logic reconfiguration, simulating and testing all possible hardware and software interactions becomes a colossal endeavor.
“Simulation solutions weren’t up to the task,” Dr. Bliss recalls. “We got the biggest FPGAs [field-programmable gate arrays] we could find, and they weren’t big enough. We needed a prototyping and emulation platform.”
Accelerating hardware and software co-design with emulation
The silicon journey on which the ASU WISCA team, University of Michigan, University of Wisconsin, and other partners had embarked took a much-needed leap forward when Dr. Bliss discovered the 草榴社区 HAPS-100 platform. The industry’s highest performance and most scalable pre-silicon prototyping system helps ensure all the pieces in a chip design — including at-speed interfaces, software, and hardware — will work together as expected in a real-world environment.
“After you design the chip, you have lots of testing and verification, and you’re trying to figure out if things are going to go your way, if all your problems are solved,” Dr. Bliss says. “But you can’t do it all in simulation.”
Specific functions and components can be tested and verified with simulation techniques and solutions, he explains, but loading Linux, booting up the entire system, and running applications on a test board is infeasible.
“It would take forever,” Dr. Bliss says. “You need emulation. There really is no other way.”
Figure 2: ASU test board. Photo by Marco-Alexis Chaira/ASU.
Optimizing system software while waiting for chips
The HAPS-100 didn’t just help Dr. Bliss and his team achieve tapeout and send their design off to a foundry. It also proved essential for maintaining productivity and optimizing system software while the chips were being manufactured.
“It can take a year or more from the time you send a design out before you get the chips back,” Dr. Bliss explains. “The HAPS-100 enabled us to continue working on the system and developing the software while we waited for the foundry.”
That included baseline Linux code, intermediate software that manages system resources, and driver-level software that interfaces with onboard accelerators.
“We couldn’t pause our programs or stop making progress for 12 to 15 months,” Dr. Bliss says. “Instead, we continued exercising the test board on the HAPS-100 and improved the speed and performance of the software by two orders of magnitude.”
An integral prototyping tool for reducing risk and enabling progress
With the manufactured chips now in hand, Dr. Bliss and his team at WISCA have moved to the next phase of system development and optimization.
“This is a scary time,” he confesses. “The chips are being placed on an interposer and then they go on the board.”
The team will address any unforeseen issues, update the design to more closely match the needs of end users, and seek additional grant funding by demonstrating current progress and future opportunity. Dr. Bliss says the HAPS-100 will help with all of it.
“Developing chips is insanely difficult. Everything in the universe wants to stop you,” he says. “For smaller players like us that don’t have unlimited resources, we need tools that can help reduce technical risk and enable progress — especially on the software side. The HAPS-100 has been absolutely critical for us in that regard, and it’s become integral to the ways we’re thinking about solutions and developing systems.”
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