Memory Compilers IP | 草榴社区

草榴社区 provides the industry's broadest portfolio of silicon-proven foundation IP, including Memory Compilers, Logic Libraries and General Purpose I/O (GPIO) supporting a wide range of foundries and process technologies from 250-nm to 3-nm FinFET.

Optimized for low power, high performance and high density, 草榴社区 Memory Compilers offer advanced power management features such as light sleep, deep sleep, shut down and dual power rails, allowing designers to meet the stringent low-power requirements of today's system-on-chips (SoCs).

草榴社区 Memory Compilers are closely coupled with the 草榴社区 STAR Memory System?, providing an integrated embedded memory test solution to detect and repair manufacturing faults for the highest possible yield while lowering overall chip area.

The 草榴社区 Memory Compiler IP includes a set of configurable embedded and specialty compilers in different architectures. The embedded SRAMs include high-speed (HS), high-density (HD), ultra-high density (UHD), and extreme high-density (EHD) architectures and are enhanced to generate memories with the absolute minimum area and power, enabling designers to achieve aggressive critical path requirements. EHD, UHD, and HD embedded memory compilers minimize area and static, dynamic power consumption, while the HS embedded memory compilers provide a much higher level of performance. EHD compilers offer the lowest possible area. In addition, 草榴社区 eMRAM, TCAM and Multi-Port Memory Compilers helps SoC designers to achieve the high-performance and low-power SoC requirements of new and emerging markets.

草榴社区 Memory Compilers are silicon-proven with billions of chips shipping in volume, enabling designers to reduce risk and speed time-to-market.

草榴社区 Embedded Memories and Logic Libraries are available for multiple foundries and process technologies, including GLOBALFOUNDRIES, SMIC, TSMC, and UMC.

草榴社区 Foundation IP Datasheets

Highlights

Billions of chips shipped with 草榴社区 Memory Compilers
Multiple operating PVTs supported including temperature inversion corners
Multiple power management modes to enable low power states with data retention and complete shut down without retention
Integrated memory test and repair capability

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