草榴社区

草榴社区 Die-to-Die IP 草榴社区

<p>草榴社区’ complete Die-to-Die IP solution includes 112G XSR and UCIe controllers and PHYs, with leading power, latency and die edge efficiency, for high-performance computing SoCs. The solution also includes HBI/AIB PHY. 草榴社区 UCIe IP, supporting standard and advanced packaging technologies, delivers up to 4Tbps bandwidth in a multi-module configuration. The UCIe controller enables an ultra-low latency link between two dies based on popular protocols and for compute-to-compute and compute-to-IO connectivity.&nbsp;草榴社区 112G XSR IP leverages high-speed SerDes technology up to 112G per lane for ultra and extra short reach links. The XSR controller includes a highly optimized FEC for a reliable, low latency link between two dies.&nbsp;草榴社区 HBI/AIB PHY, supporting the AIB 2.0 standard, leverages wide-parallel bus technology and delivers 4Gbps per pin die-to-die connectivity with low latency.</p>

Overview

草榴社区 enables multi-die designs with a comprehensive die-to-die IP solution that includes UCIe and 112G XSR controller, PHY, and verification IP. The UCIe PHY, adopted by leading companies, has achieved several silicon successes across multiple foundry processes. Operating at 40Gbps, the IP delivers maximum die-edge and power efficiency, low latency, and support for standard and advanced packaging technologies, while being compliant with the latest UCIe specification. The UCIe controller enables an ultra-low latency link between dies based on popular protocols to ensure interoperability. The 草榴社区 112G XSR IP leverages high-speed SerDes technology for extra short reach links. The XSR controller includes a highly optimized FEC for a reliable, low latency link between dies. 


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