Cloud native EDA tools & pre-optimized hardware platforms
草榴社区 IC Validator? physical verification high-performance signoff solution improves productivity for customers at all process nodes, from mature to advanced. 草榴社区 IC Validator offers the industry’s best distributed processing scalability to over 4,000 CPU cores. The tool’s performance and scalability enabled some of the industry’s largest reticle limit chips with billions of transistors, same-day design rule checking (DRC), layout versus schematic (LVS), and fill turnaround time.
IC Validator is seamlessly integrated with the 草榴社区 Fusion Compiler? RTL-to-GDSII solution and IC Compiler? II place and route system in the 草榴社区 Digital Design Family. This integrated fusion technology accelerates design closure for manufacturing by enabling independent signoff-quality analysis and automatic repair within the implementation environment.
Detects and resolves design issues early in the design process, ensuring accuracy and precision without impacting performance or yield
Complete physical verification tasks in as little as half a day with half of the compute resources typically required
Seamless integration from synthesis to signoff, enabling faster design iterations and better collaboration among teams
Listen to an insightful discussion between 草榴社区 and Cerebras Systems on the challenges facing physical verification and how to address them.
Nvidia’s Senior Manager for Hardware Engineering, Ramulu Undevalli shares how he and his team used 草榴社区 IC Validator? for physical verification and achieved significant time savings.
Intel’s Senior SoC Design Engineer, Matt Nichelson talks about the physical verification challenges his team faced and how 草榴社区 IC Validator? helped to meet those challenges with significant results.