草榴社区

Universal Chiplet Interconnect Express (UCIe) PHY IP

Our initial 草榴社区 UCIe PHY IP silicon results are back from the lab, showing robust link margins and architected for data rates of 16Gbps and scalable to 24Gbps per channel. These results were achieved in a realistic use case showing data passing through 8 modules, each implementing 64 TX and RX lanes. The IP, supporting an advanced packaging technology, shows exceptional power efficiency of 0.3 pJ/bit. In addition, 草榴社区 recently announced a successful tape out of UCIe? PHY IP on TSMC’s N3E process. 

UCIe IP is a key element of multi-die systems, allowing chip designers to achieve secure and robust die-to-die connectivity in a package while delivering high bandwidth, low power, and low latency. The 草榴社区 UCIe PHY IP offers a flexible architecture that supports advanced and standard packaging technologies, providing up to 5Tbps/mm bandwidth efficiency. 草榴社区 UCIe Controller IP supports popular protocols such as PCI Express and CXL and enables secure, low-latency NoC-to-NoC links with streaming protocols.

224G Ethernet PHY IP

草榴社区 extends industry leadership on 224G Ethernet PHY IP with our first-pass silicon success on the TSMC N3E process. Check out the image above for the 224G PAM-4 eyes with clear margins, a testament to our IP’s robust performance. As the IEEE 802.3dj defines 1.6TbE and OIF CEI-224G delves into various electrical channels, our complete MAC+PCS+PHY solution accelerates time to market for our customers’ most advanced SoCs.

112G LR-Max PHY IP

As the image above illustrates, 草榴社区 12G LR-Max PHY IP on TSMC’s N3E process demonstrates highly linear PAM-4 eyes with excellent SNDR and jitter performance. Using leading-edge analog mixed-signal design and advanced digital signal processing (DSP) technologies, the 112G LR-Max PHY IP provides additional margins to the CEI-112G LR specification and delivers three orders of magnitude better bit error rate compared to the spec for 45dB channels. The 草榴社区 Multi-Protocol 112G PHY IP is part of our high-performance multi-rate transceiver portfolio for high-end networking and HPC applications.

PCIe 5.0 PHY IP
Running at 32 GT/s with clear, wide-open eyes, 草榴社区 PCIe 5.0 PHY IP on TSMC’s N3E process successfully passed PCI-SIG 5.0 compliance testing and was the first IP to be listed on the 5.0 Integrators List. 草榴社区’ complete IP solution for PCIe consists of silicon-proven digital controllers, PHYs, Integrity and Data Encryption (IDE) Security Modules, and verification IP. As the leading supplier of IP solutions for PCIe, 草榴社区 enables cloud computing, storage, and AI accelerators to achieve low-latency, high-bandwidth requirements for real-time data connectivity.

DDR5 PHY IP
DDR is the de facto technology for system designs that require the highest capacity off-chip memory. That’s why 草榴社区 DDR5 PHY IP on TSMC’s N3E process operates up to 8400Mbps—supporting the JEDEC standard DDR5 SDRAMs and memory modules that enable workload-intensive server, enterprise, AI, and networking applications. First-pass silicon success on TSMC’s N3E process helps customers design high-performance memory solutions with faster time to market and reduced integration risks. 草榴社区 DDR5 PHY IP is part of the complete 草榴社区 DDR interface solution that includes PHYs, controllers, secure inline memory encryption (IME), IP subsystems, verification IP, and IP Prototyping Kits.

LPDDR5X/4/4X IP
The 草榴社区 LPDDR5X/4/4X PHY IP tape out on TSMC’s N3E process shows wide eyes and clear margins at 8533 Mbps and 9600 Mbps (overclocked). Optimized for power, latency, bandwidth, and area, the next-gen controller supports JEDEC standard LPDDR5X, LPDDR5, and LPDDR4X SDRAMs—and seamlessly integrates with the 草榴社区 Inline Memory Encryption (IME) Security Module to provide confidentiality of data in-use or stored in off-chip memory.

MIPI C-PHY/D-PHY IP
Running at a blistering 44Gbps, 草榴社区 MIPI C-PHY/D-PHY RX IP on TSMC’s N3E process receives high-resolution image sensor traffic up to 6.5Gbps per trio in C-PHY mode and 6.5Gbps per lane in D-PHY mode. Part of the complete 草榴社区 MIPI solution, the MIPI C-PHY/D-PHY RX IP offers seamless interoperability with 草榴社区’ ASIL B-Ready, ISO 26262-certified CSI-2 and DSI/DSI-2 controllers for automotive cameras, sensors, and displays that enable advanced driver-assistance systems (ADAS). The MIPI C-PHY/D-PHY RX IP also supports high-performance, low-power interfaces for SoCs and peripheral devices used in mobile, AI, and IoT applications.

USB-C 3.2/DisplayPort 1.4 IP
草榴社区 USB-C 3.2 and DisplayPort 1.4a IP on TSMC’s N3E process delivers a blazing 20Gbps for USB-C 3.2, 32 Gbps for DP 1.4a, or simultaneous 10Gbps for USB plus 16Gbps DP 1.4a. The IP can be seamlessly integrated into SoCs that support connections to high-definition (HD), 2K, 4K, and 8K Ultra High Definition (UHD) displays for mobile devices, set-top boxes and other applications requiring fast data transfers and output of high-resolution content. To minimize design cycles, 草榴社区 offers complete solutions for USB/DisplayPort IP implementation, including PHYs, controllers, verification IP, and IP subsystems.

eUSB2 IP
草榴社区 Embedded eUSB2 (eUSB2) PHYs on TSMC’s N3E process targets low-power mobile and consumer products such as smartphones, tablets, laptops, gaming, AR/VR, and wireless devices. eUSB2 PHY IP enables USB 2.0 connectivity using 1V or 1.2V I/O voltage in the SoC, with legacy USB 2.0 3.3V signaling provided by an external 草榴社区 eUSB2 repeater.

Foundation IP on 3nm
草榴社区 also offers Foundation IP for TSMC’s N3E process to help chip designers optimize silicon designs with embedded memories, logic libraries, and:

• Memory compilers
• High-performance core (HPC) design kits
• Power optimization kits (POK) and engineering change order (ECO) kits

草榴社区 Foundation IP on advanced TSMC process technologies is extensively proven in silicon, with billions of units shipping in volume production.