²ÝÁñÉçÇø

The ²ÝÁñÉçÇø 224G Ethernet PHY IP meets the growing high bandwidth and low latency needs of high-performance data center applications. Using leading-edge design, analysis, simulation, and measurement techniques, the ²ÝÁñÉçÇø 224G Ethernet PHY delivers exceptional signal integrity and jitter performance that exceeds the IEEE 802.3 and OIF standards electrical specifications. The area efficient PHY provides additional margin for channel loss and demonstrates zero post-FEC BER.

The PHY supports the Pulse-Amplitude Modulation 4-Level (PAM-4) and Non-Return-to-Zero (NRZ) signaling to deliver up to 1.6T Ethernet. The configurable transmitter and advanced DSP-based receiver with analog-to-digital converter (ADC) enable designers to control and optimize signal integrity and performance. The CCA algorithm provides a robust performance across voltage and temperature variations. The low jitter PLLs and multi-loop clock and data recovery circuits provide robust timing recovery and better jitter performance, while the embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance.

• Supports full-duplex 1.25 to 224Gbps data rates

• Enables 200G, 400G, 800G, and 1.6T Ethernet

• Ethernet interconnects for wired network infrastructure

• Supports IEEE 802.3 and OIF-224G standards electrical specifications 

• Meets the performance requirements of chip-to-chip, chip-to-module, and long reach copper/ backplane interconnects

• DAC-based PAM-4 transmitter includes feed-forward equalization (FFE)

• Digital-based receiver consists of analog front-end (AFE), ADC, and advanced digital signal processor (DSP)

• High-performance receiver equalization supports channel loss of 45dB 

• Continuous calibration and adaptation (CCA) provides robust performance across voltage, and temperature

• Low jitter phase-locked loops (PLLs) provide robust timing recovery and better jitter performance