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TSMC & 草榴社区
Collaborate to Innovate
Collaborate to Accelerate Innovation for Next-Generation Designs
, a leading semiconductor foundry, and 草榴社区 have joined forces to deliver optimized solutions for mutual customers across TSMC's wide range of process technologies. This collaboration offers designers access to the most comprehensive IP, EDA tools, and multi-die system design flow and Photonic IC design flows, all designed to work seamlessly with TSMC's advanced process technologies. With support for TSMC’s FinFET technology, GAA technology, COUPE technology, 3DFabric? technologies, and the TSMC 3Dblox? standard, this partnership provides designers with the tools and IPs to create cutting-edge designs that push the boundaries of what's possible.
Key Benefits
Certified Digital & Analog Design Platforms
Design complex SoCs with greater confidence
Long-Standing Collaboration
20+ years of semiconductor evolution
Minimize IP Integration Risk
草榴社区 DesignWare IP optimized for TSMC's most advanced process
Areas of Collaboration
Seamless Design Flows and Certified Design Tools
As process technologies evolve, TSMC and 草榴社区 have been proactive in anticipating design challenges that come with each new generation. We have identified new design issues and are working tirelessly to help designers navigate the increasing technical constraints and stricter production requirements. We are continuously working toward tool certification and technology for the latest nodes. Among the newest collaborations are the co-optimized Photonic IC flow and multi-die design flow, which aim to improve power, performance, transistor density and time to production, ultimately enhancing system performance. By staying ahead of the curve and working together, TSMC and 草榴社区 are leading the charge in advancing process technologies and revolutionizing the semiconductor industry.
Silicon-Proven IP for TSMC Processes
For more than 20 years, 草榴社区 and TSMC have collaborated to deliver a high-quality Interface IP and Foundation IP portfolio for TSMC’s process technologies from 180-nm to 3-nm, targeting a range of applications including HPC, AI, automotive, and mobile. With the high-quality IP portfolio, designers can align their aggressive project schedule and design requirements, while optimizing PPA, bandwidth and latency. To meet the stringent reliability and operation requirements of ADAS SoCs, leading automotive OEMs, Tier 1s, and semiconductor providers have adopted 草榴社区’ automotive-grade IP for TSMC processes. With the broad adoption of DesignWare IP and customer silicon successes, 草榴社区 enables designers to integrate the IP with confidence and significantly lower SoC integration risk.
Cloud 草榴社区 and OIP Virtual Design Environment
草榴社区 design solutions are certified for TSMC’s Open Innovation Platform Virtual Design Environment (VDE) to run on Amazon Cloud (AWS), Microsoft Azure, and Google Cloud Platform (GCP). The combination of these industry-leading cloud platforms and 草榴社区 design tools for the cloud enable system-on-chip (SoC) designs with easy hardware scaling to boost design implementation and signoff productivity.?
Design Services Partnership
草榴社区 Professional Services has created an integrated flow with best-in-class technology providers that enable us to offer a comprehensive set of chip development services for TSMC processes.
Testimonials
Our close collaboration with Open Innovation Platform (OIP)? ecosystem partners like 草榴社区 has enabled customers to address the most challenging design requirements, all at the leading edge of innovation from angstrom-scale devices to complex multi-die systems across a range of high-performance computing designs. Together, TSMC and 草榴社区 will help engineering teams create the next generation of differentiated designs on TSMC's most advanced process nodes with faster time to results."
Dan Kochpatcharin
|Head of Design Infrastructure Management Division, TSMC
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