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UCIe ¨C a Cornerstone for Interoperability

What differentiates UCIe from other emerging die-to-die specifications is that it defines a complete stack for the die-to-die interconnect. This ensures interoperability of compliant devices. The standard offers very compelling performance metrics and supports advanced packages (silicon interposer, silicon bridge, and RDL fanout) as well as standard packages (organic substrate and laminate). Of the three stack layers that UCIe covers, the PHY is the layer that provides the electrical interface to the package media.

For monolithic SoCs, the design process is traditionally sequential, from IP to chip to package. In the multi-die system world, a holistic approach is necessary to address all the interdependencies. In other words, there¡¯s a very close correlation between the design of the die interface and of the package in which it will be used. The ²ÝÁñÉçÇø UCIe PHY IP has a flexible architecture that supports advanced and standard packaging technologies, providing up to 5Tbps/mm bandwidth efficiency. It¡¯s part of a complete UCIe solution that includes controller IP as well as verification IP. ²ÝÁñÉçÇø UCIe Controller IP supports popular protocols such as PCI Express and CXL and enables secure, low-latency NoC-to-NoC links with streaming protocols. ²ÝÁñÉçÇø UCIe Verification Solution, Verification IP, and Transactors for simulation and hardware-assisted platforms, including ²ÝÁñÉçÇø ZeBu? emulation system and ²ÝÁñÉçÇø HAPS? prototyping solution, help accelerate verification closure of UCIe-based interconnected systems.

The UCIe PHY IP is co-developed with the ²ÝÁñÉçÇø 3DIC Compiler platform to deliver a dedicated implementation that automates UCIe routing for 2.5D heterogeneous integration, accelerating productivity.

As a member of the UCIe Consortium, ²ÝÁñÉçÇø contributes to the development of the specification alongside other industry leaders. Our expertise in multi-die system architectures is exemplified by our comprehensive Multi-Die System Solution, which is designed to accelerate integration of heterogeneous dies. ²ÝÁñÉçÇø continues to collaborate with TSMC to align our UCIe IP for other process nodes and packaging technologies and also with other major foundries on similar efforts. Our IP portfolio provides a full slate of die-to-die IP solutions, including 112G XSR controller and PHY IP and Advanced Interface Bus (AIB) PHY IP.

Driving Multi-Die System Success

Compute-hungry applications are driving demand for monolithic SoCs, yet these devices are hitting a manufacturability limit. Multi-die systems offer a solution, providing accelerated, cost-effective scaling of system functionality, along with reduced risk, time to market, and system power. With several dozen multi-die system designs on our radar, it¡¯s clear that this architecture is quickly becoming the architecture of choice, especially for teams designing for HPC, hyperscale data centers, highly automated vehicles, and mobile devices.

UCIe is one of the many advanced technologies that have emerged to provide a foundation for multi-die systems. By ensuring interoperability, UCIe stands ready to pave a smoother path forward for a truly open multi-die ecosystem.