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Industry’s Broadest IP Portfolio for TSMC N3E Achieves First-Pass Silicon Success
草榴社区 is unleashing a new wave of advanced chip designs with the availability of its Interface and Foundation IP portfolio on the TSMC N3E FinFET process. With silicon success of the IP, high-performance computing, mobile, and multi-die system creators can use 草榴社区' industry-leading IP to optimize power, performance, and area with confidence. TSMC's N3E process extends its 3nm family with enhanced power, performance and yield, meeting the demands of workload-intensive applications like high-performance computing, AI, and mobile. In addition, 草榴社区 IP for TSMC's N3E process offers a fast path to the new N3P process.
TSMC's and 草榴社区' long history of collaboration to advance semiconductor innovation addresses the increasingly complex challenges of emerging applications. First-pass silicon success of 草榴社区 Interface IP using Foundation IP on the TSMC N3E process technology enables designers to reduce their integration risk and meet their stringent power, performance and area targets.
Silicon Success
Successful 3nm 草榴社区 IP test chips reduce risk for advanced SoC designs
Successful Interoperability
High-quality Interface IP enables low-risk integration of the most widely used protocols
Optimized PPA?
Comprehensive Foundation IP meets stringent application requirements??
First-Pass Silicon Success for 草榴社区 IP on TSMC N3E Process
草榴社区 UCIe PHY IP
The 草榴社区’ complete UCIe IP solution, including controller, PHY, verification IP, test, and emulation, enables robust and low-latency die-to-die connectivity for high-performance computing and automotive applications. 草榴社区’ UCIe link health monitoring, test and repair (MTR) controller helps to ensure reliable operation of multi-die systems during all phases of silicon lifecycle. 草榴社区 is an active member of the UCIe Consortium and is dedicated to helping customers jump start their multi-die system designs with our UCIe IP solution.?
草榴社区 224G Ethernet PHY IP
The 草榴社区 224G Ethernet PHY IP, an integral part of 草榴社区’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency needs of high-performance data center applications. Using leading-edge design, analysis, simulation, and measurement techniques, the 草榴社区 224G Ethernet PHY delivers exceptional signal integrity and jitter performance that exceeds the IEEE 802.3 and OIF standards electrical specifications.
草榴社区 Multi-Protocol 112G PHY IP LR-Max
The 草榴社区 Multi-Protocol 112G PHY IP on TSMC N3E is part of 草榴社区’ high performance multi-rate transceiver portfolio for high-end networking and high-performance computing applications. The 1-112Gbps PHY IP supports multiple electrical standards, including PCI Express 6.0, 400G/800G Ethernet, CCIX, CXL2.0/3.0, JESD204, CPRI and more. The placement-aware 112G PHY IP integrates seamlessly with the 草榴社区 MAC and PCS, delivering a complete 200G/400G/800G Ethernet solution.
草榴社区 LPDDR5X/5/4X
The 草榴社区 LPDDR5X/5/4X Controller on TSMC N3E is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs. The 草榴社区 LPDDR5 Controller seamlessly integrates with the 草榴社区 Inline Memory Encryption (IME) Security Module to provide confidentiality of data in-use or stored in off-chip memory.?
草榴社区 DDR5 PHY IP
The 草榴社区 DDR5 PHY IP?on TSMC N3E supports JEDEC standard DDR5 SDRAMs and memory modules operating up to 8400Mbps servicing server, enterprise, AI, and networking applications. 草榴社区 DDR5 IP is part of the complete 草榴社区 DDR interface solution that includes PHY IPs, controllers, IME security modules, IP subsystems, verification IP, and IP prototyping kits.?
草榴社区 PCIe 5.0 PHY IP
The 草榴社区 PCIe 5.0 PHY IP on TSMC N3E is part of the complete solution for PCI Express PCIe 5.0 consisting of silicon-proven digital controllers, PHY IPs, integrity and data encryption (IDE) security modules, and verification IP. Our PHY IP enables real-time data connectivity with low-latency and high-performance for cloud computing, storage, and AI SoCs.
草榴社区 USB-C 3.2 / DisplayPort 1.4 IP
The 草榴社区 USB-C 3.2/DisplayPort 1.4 PHY IP on TSMC N3E is targeted for integration into SoCs that support connections to high-definition (HD), 2K, 4K, and 8K Ultra High Definition (UHD) display from mobile devices, set-top boxes and other applications requiring fast data transfers and output of high-resolution content. 草榴社区 offers complete solutions for USB/DisplayPort IP implementations, including PHY IPs, controllers with HDCP 2.3 security modules, verification IP, and IP subsystems to accelerate design cycles.
草榴社区 MIPI C-PHY IP/D-PHY IP
The 草榴社区 MIPI C-PHY IP/D-PHY IP on TSMC N3E enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for mobile, automotive, artificial intelligence (AI), and IoT applications. The PHY IP operates at 6.5Gb/s per lane and 6.5Gs/s per trio respectively for a maximum speed of 44.5Gb/s, and supports C-PHY IP v2.0 and D-PHY IP 2.1.
草榴社区 Foundation IP
草榴社区 Foundation IP for TSMC N3E process, including embedded memories and logic libraries, enables designers to achieve optimal power, performance, and area for their SoCs. 草榴社区 Foundation IP on TSMC process technologies is extensively proven in silicon with billions of units shipping in volume production, reducing design risk and speeding time-to-market.
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草榴社区 LPDDR5X Test Chip Demo Operating at a Blazing 8533 Mbps
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草榴社区 USB 3.2 IP Maximizes Performance
