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Unlocking Compute Performance with Advanced Technology

Unlocking the Potential

The most advanced silicon processes provide fast, dense, highly power efficient digital logic. The combination of process with advances in the Arm architecture have driven up compute performance. This comes with a rise in the required memory bandwidth and has resulted in increasing complex cache hierarchies with increased on-die SRAM capacity. While logic has continued scaling, in recent years the SRAM density scaling has slowed. This has increased the cost of on-die SRAM, when compared to logic.

Advanced 2.5D and 3D chip-to-chip interconnect fills the ¡®pitch gap¡¯ between the PCB and on-die interconnect. To take advantage of this, Arm is developing architectures for compute subsystems to facilitate partitioning into chiplets, allowing systems to scale seamlessly across multiple dies. This allows high performance compute systems, such as cloud servers, to grow beyond the reticle limit, as well as use the process nodes best suited for each part of the system.

Looking to the Future

As 2.5D and 3D advanced packaging becomes deployed more widely into a broader range of products, we enter a feedback loop. High volume increases yield and reduces cost, which enables new system partitions to address additional use cases. Interesting opportunities emerge to utilize the latest process nodes for advanced compute, while continuing to increase SRAM capacity in a cost-efficient way.

In the future, we believe systems composed of co-packaged chiplets will become widespread across the industry. Companies will be able to amortize their hardware and software engineering investment by reusing chiplets for multiple products. Complex systems will be cleanly partitioned, reducing risk, cost, and time to market.

Re-use of effort is at the core of the foundry and silicon-IP business models. This remains the key enabler which allows exciting new products to be put into the hands of consumers in a cost-efficient way. Standardization is crucial to enable a truly interoperable chiplet ecosystem. Besides process and die-to-die interconnect technologies, suitable system architectures and IPs are required to provide composability through to the higher-level software interfaces. Arm looks forward to working with our industry partners to enable this future.

Our Vision: Creation of an OPEN Ecosystem for Automotive SoCs based on Chiplets from Numerous Vendors

Future Vehicle Computers Require Enhanced Capabilities

These systems present high computation demands for central data processing with a wide range of functional integration. Examples include central software-driven platforms with service-oriented architectures, multiple operation systems, and a variety of safety, timing, and security demands.

There is a need for rapid update and innovation cycles with generation intervals of about two years. We see scalability demands across different models and with individual feature sets.

High-performance SoCs (especially for ADAS/AD and Infotainment) Present Challenges and Opportunities

The optimization potential (performance, power, etc.) by technology carries over from consumer electronics or HPC designs at OEMs. However, there is insufficient scalability of SoCs across all vehicle classes and functions (e.g., from NCAP to SAE L4). The lack of resilient supply chains contributes to the problem.

To Overcome These Obstacles, a Requirements-driven Open Ecosystem is Needed

Automotive SoCs based on chiplets from numerous vendors provides the required level of flexibility and sophistication. A customized automotive chiplet system (ACS) can be based on design approaches proven in nonautomotive, high-performance SoC design.

This will allow the break-up of a monolithic system into separate integrated circuits on multiple dies, integrated by advanced packaging technologies to comprise a high-performance compute unit.

What is needed is a market environment where system OEMs can reduce lead time to configure specific individual automotive chiplet systems, based on a chiplet offerings and related software and tooling from various suppliers.

Key Characteristics of this OPEN EcoSystem:

• Interfaces, connections, and standards are clearly defined within the ecosystem
• Each value chain step is supported with a multitude of players that produce similar chiplets
• This approach delivers the highest degree of modularization and co-creation to enable best, scalable products

The AI Revolution and Co-Design with Chiplets

The AI Revolution: The Challenges Ahead

The AI revolution is just getting started. Beyond large language models and generative AI, there is a lot of new innovation ahead in AI and ML. This accelerated pace of innovation on exponential volumes of data means a correspondingly profound increase in compute requirements.

But supply is not keeping up with this demand. Moore¡¯s law, which underpinned our computing innovations is slowing down. Chip geometries can no longer shrink at the rate we assumed they would. We are seeing generation-to-generation power and performance improvements slowing down drastically.

Put together, we need much more compute power than ever before, and traditional technology approaches do not support this growth. We have to evolve faster! We need to revolutionize how we develop chips.

The AI Revolution: The Opportunities Ahead

It is time for a new framework to deliver advanced computing, to rewrite the rules of hardware innovation, creating harmony between hardware and software.

System-level optimization or co-design where we look at the whole stack ¡ª from the application level all the way down to the chip level ¡ª can achieve dramatic benefits. Our  and  have both adopted this approach to  meet the growing demand for machine learning and video distribution services at Google.

We must look beyond traditional logic design and embrace modularity to take advantage of chiplets and packaging solutions. Chiplets allow us to do co-design in a multi-die system context, allowing cost advantages but also mix-and-match integration across heterogeneous IP blocks.

There are a lot more pieces of the puzzle that will need to come together ¡ª across cooling, testing, standards, etc. ¡ª but one thing is sure: there is going to be a lot of innovation in the next few years ahead. We are just getting started!

The Future of Multi-Die Systems Lies in Silicon

Enabling Advanced Products with Multi-Die

In the pursuit of the greater functional integration of Moore¡¯s Law, 3D-IC integrates the silicon content within a package. With more functionality integrating within a package, where the system essentially collapses into the package, the amount of silicon exceeds that which can be built within lithography reticle limits.

The functionality must be split across multiple silicon components, with advanced packaging techniques providing low latency, low power, high bandwidth interconnections between the multiple chiplets

System-Technology-Co-Optimization (STCO), the next major evolution of innovation in Moore¡¯s Law, starts tops down with application workloads and optimizes performance for those workloads with semiconductor technology vectors, multi-die chiplets, and advanced packaging interconnects.

STCO framework provides the optimized heterogeneous integration of each chiplet¡¯s design and silicon process features, cost, functionality, IP block availability, and with advanced packaging delivers optimized System-in-a-Package solutions.

Enabling the Ecosystem with Advanced Packaging

Advanced packaging plays a critical role in enabling multi-die products. Heterogeneous integration using advanced 2.5 and 3D packaging technologies, like EMIB and Foveros, offers an attractive path to architecting products by combining chiplets from various sources, designed on disparate silicon nodes.

This mix and match capability unlocks the ability to optimize for unique functionality, performance, and cost while enabling reuse and modularity.

With this strategy there comes a key paradigm shift wherein packaging is now a key part of the overall co-optimization of the product system design. An important part of making an open chiplet ecosystem of multidie integration more streamlined is standardization covering a multitude of elements, including die-to-die interfaces, design tools, mechanical specifications, and manufacturing equipment.

The Universal Chiplet Interconnect Express (UCIe) standard is one such standard and a crucial step in enabling the rich and robust industry ecosystem needed. On top of this, electronic design automation (EDA) tools need to use standard file formats to enable seamless design among silicon, packaging, and system boards.

Heterogeneous Integration Platform for Next Generation Computing ¡°Road to Beyond Moore¡±

Breakthroughs in AI, 5G, autonomous vehicles and Metaverse tech promise to reshape the way we live ¡ª but delivering the function and performance needed to power those advancements on a single chip is becoming more complex, and less cost-effective.

Advances in heterogeneous chip packages are needed to empower today¡¯s device manufacturers to pursue tomorrow¡¯s breakthroughs. Both 2.xD and 3D variations will be needed to keep innovation vibrant.

Below are examples of how Samsung combines chips, process nodes, and cutting-edge tech to open new possibilities.

I-Cube 2.xD Package

2.xD packages deploy parallel horizontal chip placement to combat heat build-up and expand on performance. I-Cube Platform enables larger interposer, more HBMs and multi-die for AI/Data Center applications.

The I-CubeS based on Si-interposer brings impressive bandwidth and stunning performance capabilities to the table with emphatic warpage control, even with large interposers. And the I-CubeE has Si embedded structure which covers advantages of both Si-bridge by fine patterning and RDL interposer with TSV-less structure.

X-Cube 3D IC

3D IC packages save massive amounts of on-chip real estate by stacking components vertically, reducing surface area and bumping performance by shortening the space between chips. By dramatically reducing the risks from big die construction, they keep costs low while retaining high bandwidth and low power performance. X-Cube is a full 3D solution, which allows the v ertical stacking of chips.

X-Cube comes in two different forms: Two vertically stacked dies are connected either with micro bumps, or by bump-less hybrid Cu-Cu bonding (HCB). The HCB have a lot of advantages from the view-point of layout flexibility compared with the conventional chip stacking technologies.

Advanced Package Solution Service

Samsung launched a new advanced package (AVP) business unit for the increasing importance of Advanced Packaging. Build your way with endto- end packaging solutions. Your products are unique. So are the chips that power them. Samsung AVP will provide flexible services to customers leveraging Samsung semiconductor¡¯s synergy platform. Samsung HI Ecosystem ensures deep collaboration between the Samsung AVP, ecosystem partners, and customers to deliver competitive and robust Advanced Package.

Why Multi-Die Systems, Why Now?

At the very core of the movement to multi-die systems is the insatiable thirst for faster, better, and smarter. The drive to cram more and more functionality, and with that more user experiences into products and services. For many years, Moore¡¯s law-driven scalability met these needs.

However, device scaling is slowing and the benefits of moving to newer nodes are diminishing while costs are increasing ¡ª trends that will continue as we get into the Angstrom era. Yet the drive for compute, further fueled by ubiquitous AI is creating immense demand for highly complex and increasingly heterogeneous systems to address functionality and user experience needs.

The situation presents a perfect storm. If the chips can¡¯t scale as an answer to the growing compute-density and functionality demands, and the market demands these complex systems ¡ª we need a different answer. And that answer is multi-die systems.

How Real is the Multi-Die System Trend?

Simply put, it¡¯s very real and it¡¯s happening now. ²ÝÁñÉçÇø works with many advanced system OEMs to develop next-generation semiconductor designs. We¡¯ve already worked with quite a few customers to integrate multiple dies into a single package.

The economic benefits of a multi-die system approach include re-use of proven chip technology to create multiple SKUs in a product family. Large designs that approach the reticle limit, or maximum die size suffer from low yield, resulting in high silicon cost. Decomposing a large design into smaller chips results in much better yield and associated silicon cost.

From a physics perspective, ubiquitous sensing, analog processing and many types of communication don¡¯t benefit from advanced scaling. A system composed of optimized blocks, built with the optimal process technology presents a better alternative.

In November 2022, ²ÝÁñÉçÇø held its yearly Global User Survey. 6,025 people responded to the survey which touched on many design and technology trends. The companies responding had a worldwide footprint and the respondents came from a broad range of job categories and disciplines.

A question regarding multi-die system usage revealed a strong adoption trend. The question asked respondents about plans to use 3D-IC technology, including thru-silicon vias (TSVs). Over 50% of respondents were either using or planning to use this technology.

How Does the Multi-Die System Approach Impact the Design Flow?

All of the challenges faced in monolithic 2D chip design still must be addressed for multi-die systems. But the scale is much larger. The potential interactions between parts of the system are also greater. There are complex thermal and power management challenges within the package, architectural partitioning, and partitioning for the massive software stacks that interact with the hardware for example.

The multi-die system journey begins with partitioning between hardware and software. Each of the dies in a muti-die system could have its own software stack. And verifying this software in the context of the hardware it¡¯s going to run on is important. ²ÝÁñÉçÇø has very successful solutions available for monolithic 2D chip design, and we¡¯ve expanded those to enable the more complex verification problem presented by multi-die systems.

We have solutions like Platform Architect for early functional architectural exploration, and Virtualizer with the largest System C IP library to enable efficient virtual prototype assembly. And the HAPS prototype system, which delivers high-speed I/O verification as well as mixed voltage support. We offer the ZeBu and ZeBu Hybrid emulation platforms with very high scalability, which can handle the many use cases encountered in a complex multi-die system.

There are also unique power and thermal challenges. These become firstorder effects and must be analyzed very early. To address this need we¡¯ve partnered with Ansys to bring their best-in-class solutions for signal, power and thermal integrity into the design flow, alongside ²ÝÁñÉçÇø¡¯ golden signoff solutions, PrimeTime and StarRC. This is all delivered with the 3DIC Compiler solution that provides a unified platform to integrate tens to hundreds of heterogeneous dies in an optimized system for performance, power, and thermal effects.

Beyond design tools and methodology, IP is a critical enabler for multi-die systems. IP that fuels chiplet design and IP that facilitates communication between the dies in a muti-die system. ²ÝÁñÉçÇø has the broadest IP portfolio in the industry with leading offerings across many titles, including a comprehensive die-to-die IP solution.

As we approach the end of the design process, system testability and reliability become important. The challenge here is not just taking all known good die and putting them together in a single package, it¡¯s about ensuring the health of the system all the way through its lifecycle, including in-field operation.

²ÝÁñÉçÇø has many solutions here like the extended TestMAX, as well as a portfolio to support silicon lifecycle management with tools, in-chip monitor IP and analytics to help the system through its journey in the field with reliability and security.

So, the entire multi-die system design journey is covered from early architecture, to physical design and verification to deployment in the field.

Where Do Chiplets Fit?

The term chiplet has many meanings. In general, a chiplet represents a bare-die version of a chip design that can be integrated with other components using high-density integration methods to form a complete system in a package. Chiplets can be used to implement small functions such as sensors all the way to large processor arrays that are as big as large monolithic designs.

For example, a popular use case is I/O disaggregation where compute engines are in one die and I/O are in a separate die. Enabling effective use of chiplets requires focus in two areas.

One is standardization of use cases for chiplets, such as the work being done by UCIe. This work addresses aspects such as electrical parameters, compliance with other standards, interoperability, and form factor.

The other is the supporting methodology, such as top-level partitioning, software development, testability, and silicon lifecycle management.

Both areas are important for the development of an industry-level chiplet ecosystem.

At ²ÝÁñÉçÇø, we have the IP, the IP subsystems, the tools, methodologies and flows to help enable a chiplet ecosystem. We are also working with organizations such as the ODSA, part of OCP and the UCIe Consortium, along with all their partners and members to address the technical and the business challenges so multi-die systems can have broader adoption across the market.

²ÝÁñÉçÇø is also introducing AI into the multi-die system design flow to deliver step-function improvements in design efficiency and quality of results.