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Since multi-die systems aim for significantly more functionality in a much smaller footprint than their monolithic counterparts, performance per watt is the key attribute denoting how efficient the systems are. Integration of multiple components, however, creates several challenges related to thermal stress. Much higher transistor density generates a lot of heat. The architecture leaves little room to dissipate heat. And if the heat isn¡¯t dissipated, die function could be hampered by mechanical stress or warping if temperatures go beyond the optimal range for the device.

Heat sinks and other cooling structures in the multi-die system can help, though these components do add to the device area and cost. Designing the power grid to ensure that enough power is supplied to all areas of the system also becomes more complex in a multi-die system architecture.

A well-planned architecture following an iterative process can alleviate thermal stress. Following the initial architecture and physical planning, the team can analyze the resulting thermal behavior. Then, they can revise the architecture and perform physical planning to improve the thermal behavior. Iterations continue until the thermal constraints, along with performance requirements, are satisfied.

As part of this iterative process, ¡°what if?¡± exploration at the front end helps avoid getting locked into a partitioning structure that could eventually turn out to be sub-optimal from a power perspective. System architecture teams can use modeling tools to abstract out pieces of their chip into models for performance analysis and implementation of power tradeoffs before the design is locked into its partitions. By mapping a workload onto a multi-die system, the design team can determine the activity per processing element and per communication path. Modeling the hardware and software together also becomes more critical to generate a design that¡¯s fundamentally robust and thermally sound, since each die in the design will have its own software stack. Continued monitoring during the RTL, synthesis, place and route, and other design steps is also valuable. As tool flows evolve to become more thermally aware, this process will become more automated.

From a thermal standpoint, embedding sensors in each die to monitor and regulate health on an ongoing basis (silicon lifecycle management technology) provides indications on whether to, for instance, dial down performance to cool down the system. In-chip sensors are commonly used in applications like automotive and mobile and are likely to become mainstream practice for applications like HPC and AI.

While multi-die systems are an answer to increasing systemic and scale complexities, they do have inherent design challenges that engineering teams need to address. This is to be expected in a system with tens of chips, high integration densities (typically 10,000 to up to one million I/Os per mm2), and 3D heterogeneous designs and hybrid architectures. An important step is to explore scalability options and architectures to achieve optimal PPA/mm3. And an important approach is to co-optimize the full system for PPA, physical constraints, and cost.

When it comes to validation, it¡¯s much too simplistic to consider a multi-die design as being a much larger system than an SoC. It is, but effectively emulating very large systems brings capacity into question. Multi-die systems also tend to be heterogeneous, with dies developed on different process nodes and, in some cases, reused, limiting access to any proprietary RTL.

For multi-die software development and software/hardware validation, there are a few key considerations and solutions:

• Software bring-up of one die with software dependency on other dies. Multi-abstraction system modeling can leverage fast, scalable execution platforms that make use of virtual prototyping and hardware-assisted verification.
• Validation of the die-to-die interface. Pre-silicon validation can take advantage of IP blocks verified and characterized using analog/mixed-signal (AMS) flows. Pre-silicon validation and compliance testing can also be handled via a UCIe controller IP prototype with a UCIe protocol interface card.
• Multi-die system software/hardware validation. Each die can be mapped onto its own emulation setup and connected via die-todie transactors (UCIe, etc.). Realistic application workloads executed with hardware-assisted verification can yield insights into multi-die system performance and support fast turnaround time on power validation. A die under test can also be connected via a speed adaptor to prototypes of mature dies.

Let¡¯s dive in a little deeper on these points. Given such a complex system running very complex software, it¡¯s essential to start the validation process early, creating virtual prototypes of the multi-die system to support software development. Specifying system behavior up front with a virtual model, running software on that model, allows the system specs to become more solidified and the software to become better defined before emulation.

In multi-die systems, it¡¯s important to optimize the die-to-die connections at the protocol level (the digital parts) and the analog level (the PHY). AMS emulation helps to reduce the risks that something will go wrong post-silicon.

Heterogeneous setups can facilitate validation of multi-die systems. Consider a design consisting of three dies developed by one semiconductor supplier, who provides the RTL, and a fourth die from another supplier, without RTL access but with an existing die. The three dies with RTL can be emulated in a large-scale setup with UCIe transactors providing the bridge between different emulators, actually representing the connectivity in the actual multi-die system. The fourth die could be packaged in a test chip on a test board that connects to the emulator through a UCIe speed adaptor. With capacity concerns addressed, emulation can then support debugging and validation of the design¡¯s software with its hardware. Through this process, teams can get the guidance needed to make the right decisions. For example, by determining the power consumption of each die in a system early on, the team can determine whether die stacking is feasible based on the power budget of each die.

Whether we¡¯re talking about a single-die or multiple dies, the entire system must be validated to ensure that it is functionally correct vis-¨¤-vis its design specifications. In other words, does the design do what it is intended to do? Individual dies are verified before they¡¯re assembled together. More exhaustive verification at the die level reduces the chance of multi-die system bugs. After assembly, however, tests must be performed at the connectivity level to ensure that data pushed through one port lands in the right place and at the system level to ensure proper system performance.

As EDA vendors continue to enhance tool flows, the design community can look for investments in areas to address the verification challenges of multi-die systems. For example, cloud-based hybrid emulation that takes advantage of the cloud¡¯s elasticity could address capacity concerns. Transaction-level capture that streams only relevant data quickly over the cloud from distributed nodes, to be analyzed together later, could make debugging of large systems manageable. Distributed simulation techniques that repurpose multiple nodes in a cloud to use, say, 1,000 cores in the network for parallel simulation could accelerate multi-die system verification.

Design signoff is a multi-step process that involves going through an iterative series of checks and tests to ensure that the design is free of defects before it is taped out. Signoff checks are complex, covering areas such as voltage drop analysis, signal integrity analysis, static timing analysis, electromigration, and design rule checking. Multi-die system signoff follows a similar methodology, but on a much more massive scale given all the system interdependencies.

An efficient and comprehensive extraction flow can model various multi-die system architectures for accurate performance and silicon results supporting advanced process technologies. Engineering change orders (ECOs) for multi-die systems need to be executed fast and in concert with all the ecosystem partners involved, so that changes can be identified quickly and designs can be reconciled efficiently. This can only be done with golden signoff tools that offer comprehensive and hierarchical ECO that can also accelerate PPA closure. In addition, being able to accurately analyze your multi-die system design helps find problems prior to tape out. Golden signoff tools can provide the assurance that each parameter in a multi-die system can be closed with accuracy, completeness, and expediency