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Speed Software Development, Hardware Verification, and System Validation
The 草榴社区 HAPS? prototyping solution accelerates software development, hardware verification, and system validation for everything from IP blocks to complete SoCs. Trusted across the electronic supply chain by IP, semiconductor, and system companies, HAPS combines proven hardware platforms and optimized software, delivering top performance and reliability with over 20 years of FPGA synthesis expertise from the 草榴社区 Synplify? product line.
What's New
News Release
February 13, 2025
Announcing the Industry's Highest Performance Hardware-Assisted Verification Portfolio
Video
Unveiling Next-Gen Zebu & HAPS: Hardware-Assisted Verification 草榴社区 for Emulation & Prototyping
Tools and Ecosystem
HAPS ProtoCompiler SW
HAPS ProtoCompiler software helps the prototyping team create the fastest performing implementation of their design on the HAPS prototyping hardware. It enables the prototype to find both the optimum partitioning between the FPGAs and the best connectivity using the HapsTrak3 cable. ProtoCompiler uses its proven timing-driven synthesis engine to create a performance optimized prototype. ProtoCompiler is used for runtime and debug, and feeds into the 草榴社区 Verdi? debug environment. Key features include:
Performance Optimization
Constraint-driven partitioning and high-speed time-domain multiplexing maximize system clock performance
Optimized Partitioning
Optimizes partitioning between FPGAs and connectivity using HapsTrak3 cables
Timing-Driven Synthesis
Employs a proven timing-driven synthesis engine to handle complex clocking structures
High Capacity
Supports billion ASIC gate capacity for scalable SoC/ASIC projects
Flexible Debug Options
High-capacity storage options for single or multi-FPGA debug enhance observability and sample rates
Unified Debug Approach
Integrates with the industry-standard Verdi debug solution for efficient error analysis
Joint Debugging
Enables joint debugging by RTL verification engineers and prototypers, saving valuable project time
Hybrid Prototypes
Arm AMBA compatible transactor level interfaces facilitate hybrid prototype implementation
HAPS Accessories
HAPS users benefit from a variety of add-on cards and accessories from 草榴社区 and HAPS Connect partners, including:
- MGB Board: Interfaces standard MGB cards with the HapsTrak connector.
- GPIO+ Board: Facilitates debugging and basic interactivity through buttons and LEDs.
- QSFP+ Board: Supports protocols like QSFP+, 40G Ethernet, and SAS.
- HAPS Logic Analyzer Interface Board: Enables signal probing with standard logic analyzers.
- LPDDR4 Memory Board: Aids in prototyping designs with LPDDR4 memories.
- HapsTrak3 (HT3) Interconnect Board: Facilitates point-to-point connections between FPGAs.
- External Clock Distribution Board: Synchronizes clocks across up to six HAPS systems.
HAPS Ecosystem
The HAPS Connect program provides a wide range of third-party accessory boards and services that enhance the functionality of HAPS systems. If you're interested in becoming a HAPS Connect member to supply accessory cards to thousands of HAPS users, please contact us at hapsconnect@synopsys.com.
e-Elements
- : This daughter board includes two micro-USB connectors, 20-pin Arm debug interface, 38-pin MICT, and 28-pin PMOD.
- : Features Micron NAND Flash and SDIO for access to general-purpose nonvolatile devices.
- : Contains a TSOP56 NOR Flash device socket.
- : Supports up to 8 high-speed serial links over 2 FireFly cables.
- : Includes an FMC connector to interface with 3 FireFly connectors, supporting up to 10 high-speed links.
- : Based on a TI TUSB1310 device with ULPI for USB 2.0 and a PIPE interface for USB 3.0 support.
Fidus
- : Contains the Xilinx Zynq UltraScale+ ZU19EG, supporting a quad-core Arm processor and up to 32Gbps links.
Gigafirm
- : FPGA module board with an Intel MAX10 FPGA. I/O pins on a 2.54mm pitch header for various embedded applications.
- : Used to cross-convert signals from the HT3 connector or cable.
- : A 12-lane MPO connector for short-reach applications up to 100m on OM3 multiple fiber cables.
Explore the Industry Leading Product Family
HAPS prototyping solution offers an integrated prototyping flow. HAPS-200 is the flagship product and targets the most complex designs with the highest performance requirements. HAPS is supported by an ecosystem of third-party vendors from the 草榴社区 HAPS Connect program that provides accessory card interfaces for HAPS.
What Our Customers Are Saying
"With the increasing market requirements for handling large AI computational data sets driving the need for enormous GPU and CPU computational power, the development time for NVIDIA’s next generation AI systems have become highly compressed to a yearly release cycle, necessitating best-in-class prototyping solutions. 草榴社区 HAPS-200 offers the fastest prototyping speed in the industry. The 50 MHz performance we have been able to achieve with HAPS-200 has been key to boosting productivity of our software development teams. We are looking forward to scaling our HAPS-200 deployment to take full advantage for our software development teams.”
Narendra Konda | Vice President, Hardware Engineering, NVIDIA
"The future of emulation and prototyping demands unprecedented performance, adaptability, and scalability. By integrating the AMD Versal Premium VP1902 adaptive SoC, with its industry-leading capacity*, performance, and debug capabilities, into 草榴社区' EP-Ready platforms we're not only improving performance metrics, we're also transforming how engineering teams can validate and optimize their most ambitious new ASIC and SoC designs. Our longstanding partnership with 草榴社区 empowers design teams to tackle their most complex verification challenges, from AI/ML workloads to multi-die architectures, while dramatically accelerating time to market.”
Salil Raje | Sr Vice President and General Manager, Adaptive and Embedded Computing Group, AMD
*Based on AMD internal analysis in May 2023 with a 6-input LUT count to compare the Versal Premium VP1902 device versus competitor offerings.
“草榴社区 is a key member of Arm Total Design, bringing critical tools and the advanced HAV capabilities to quickly and reliably validate solutions built on Arm Compute Subsystems (CSS). The new ZeBu-200 and HAPS-200 hardware platforms will also assist our mutual customers in integrating Arm CSS into their designs with improved turnaround times to meet the demanding requirements for complex data center infrastructure and automotive systems.”
Kevork Kechichian | Executive vice president, 草榴社区 Engineering, Arm
"Extending the modular HAV capabilities to the ZeBu Server 5 platform provides a scalable emulation roadmap to address the complexity challenges of validating AMD’s largest next-generation devices.”
Alex Starr | Corporate Fellow, AMD
“SiFive has a very large and configurable portfolio of RISC-V CPU and AI core IP. We extensively test our IP using software workloads on HAPS, which means we can run trillions of cycles per day. As next generation CPUs and AI cores become larger and more complex, we need to efficiently map them onto larger and more powerful FPGAs. With its EP-Ready hardware HAPS-200 offers us an FPGA platform to do full system emulation for reference platforms that scale from small microcontrollers all the way to large scale data center designs.”
Albert Huntington | Vice President, Platform Engineering, SiFive
"AMD has used ZeBu EP solutions for fast emulation with software workloads for a number of years. The EP-ready Hardware concept has allowed us to switch on demand, as a design matures, to a prototyping use case and significantly increase workload throughput. ZeBu-200 and HAPS-200 EP-Ready systems will enable further performance improvements to accelerate design verification and software validation."
Alex Starr | Corporate Fellow, AMD
"Validating our multi-die design against real-world interfaces and scenarios with the high-performance HAPS prototyping platform enables us to optimize our design early on, with faster build times and more predictable results. Having a common hardware platform for different prototype models means we can shift the hardware to use on large or small models in real time, with reduced compute and storage resources and the ability to easily and quickly scale as our needs require."
Lam Ngo | Principal Engineer, Microsoft
Resources
Video
SiFive Discusses RISC-V SW Validation and Prototyping