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IC design is a critically important discipline. It forms the basis for the development of all microelectronic devices in use today. This includes the microprocessors that power laptop computers and cell phones, the image processing circuits that power computer monitors and television sets, and the sensors that are used in wearable and implanted medical devices. These microelectronic devices also allow the growing use of artificial intelligence (AI) that is opening new frontiers, such as autonomous driving, machine vision, and natural language processing. 

IC technology deployment has become widespread in our world, and IC design forms the foundational set of disciplines required to create these devices.

The process of IC design can be thought of as a series of hierarchical decomposition steps. High-level requirements are decomposed into more details with the goal of implementing a circuit on a silicon wafer that faithfully performs the objective function. The primary steps that make up an IC design flow include:

• Architectural Design. Here, the required functionality of the IC is specified. The capabilities of the specific IC being contemplated will be considered in the context of the system being built. What functions must the IC deliver? What is the required speed and power consumption? What is the target cost of the device?  The answers to these questions will inform subsequent choices for the specific technology that will be used to implement the device. At this stage, “what” is required is most important.  “How” it will be implemented is still not well defined.
• Logic/Circuit Design. Here, macro-level building blocks are assembled and interconnected to implement the required functionality of the IC. Typically, pre-existing building blocks are used, such as memories, processing units, and sensors. High-level functional descriptions of circuit elements are decomposed into the required low-level circuit elements. This process is automated by software called logic synthesis. The collection of devices is simulated to verify the functionality of the design.  Either a digital logic simulator or an analog circuit simulator will be used, depending on the level of simulation detail that is required. If the macro-level building blocks need to be modified to achieve the requirements of the IC, custom circuit design techniques are used. During this step, “how” the chip will be implemented begins to be defined.
• Physical Design. During this step, the actual layout of the interconnected shapes that implement all the required circuit elements on the silicon wafer are created. The process begins with a chip “floor plan,” which defines where each of the primary functions of the chip will be located and where the primary input and output ports of the design will be located. The final circuit elements are then placed and routed in preparation for manufacturing. If the macro-level building blocks need to be modified to achieve the requirements of the IC, custom layout techniques, employing an IC layout editor tool, are used.  “How” the chip will be implemented is now fully defined.
• Physical Verification. All of the physical effects that the manufacturing process adds to the design can now be modeled. Added resistance from wiring, signal crosstalk, and variability in the manufacturing process itself are some of the many items that must be considered here. Will the circuit still work correctly under these stresses? In addition, there are many design rules regarding how the circuit must be physically laid out on the silicon wafer to ensure it will be manufacturable. These design rules are checked at this step as well.
• Signoff. This is the final step before the design is sent to manufacturing. Here, all of the critical parameters that will impact the performance or manufacturability of the chip are verified against the results of “golden signoff” quality tools. Design rules are fully verified during this step, along with design for manufacturability rules.  The timing, power consumption, and signal integrity of the design are also verified and “closed” during this step. It is critical that accurate parasitic extraction is performed during signoff to ensure the physical effects of the process are well understood. The golden signoff 草榴社区 tools used during this step include IC Validator, PrimeTime?, PrimePower, and StarRC.

When one considers advanced semiconductor technology, there is another aspect of the IC design flow that becomes important. In advanced manufacturing technology, physical effects and process variability play a major role. For example, the physical resistance of the wires that connect circuit elements can cause significant changes in operating voltages and, thus, overall circuit performance. The variability of the manufacturing process can also create unexpected circuit behavior. To deal with these issues, late effects such as wiring delay and process variation must be modeled and considered early in the design process to ensure these effects are accounted for.

In addition, some aspects of the design, such as how it will be tested and how much power it will consume, need to be modeled and refined at each step of the process. These items are too complex to be dealt with at the end of the design. This process of “looking ahead” is called a Shift-Left approach, and it requires a very sophisticated set of design tools and design flows to support it.