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Electronic Design Automation is primarily a software business. Very sophisticated and complex software programs function primarily in one of three ways to assist with the design and manufacture of chips:

• Simulation tools take a description of a proposed circuit and predict its behavior before is it implemented.
• Design tools take a description of a proposed circuit function and assemble the collection of circuit elements that implement that function. This is both a logical process (assemble and connect the circuit elements) and a physical process (create the interconnected geometric shapes that will implement the circuit during manufacturing). These tools are delivered as a combination of fully automated and interactively guided capabilities.
• Verification tools examine either the logical or physical representation of the chip to determine if the resultant design is connected correctly and will deliver the required performance.

While most EDA products are delivered as software, there are some cases where physical hardware is also used to deliver capabilities. Hardware is typically used when extremely high performance is required. This occurs when a large amount of data must be processed during simulation and verification. In all cases, a dedicated hardware model of the circuit will perform far faster than a software program executing the same model. This dramatic increase in speed is often required to complete various tasks in reasonable amounts of time (hours to days vs. weeks to months). The two primary delivery vehicles for EDA hardware are emulation and rapid prototyping.

Simulation

Simulation tools take a description of a proposed circuit and predict its behavior before is it implemented. This description is typically presented in a standard hardware description language such as Verilog or VHDL.  Simulation tools model the behavior of circuit elements at various degrees of detail and perform various operations to predict the resultant behavior of the circuit. The level of detail required is dictated by the type of circuit being designed and its intended use. If a very large amount of input data must be processed, hardware approaches such as emulation or rapid prototyping are used. These situations occur when a processor¡¯s operating system must be run against real-world scenarios, such as video processing. Without a hardware-assisted approach, the runtime for these cases can be untenable.

Design

Design tools take a description of a proposed circuit function and assemble the collection of circuit elements that implement that function. This assembly process can be a logical one where the correct circuit elements are chosen and interconnected to implement the desired function. Logic synthesis is an example of this process. It can also be a physical process where the geometric shapes that implement the circuit in silicon are assembled, placed, and routed together. Broadly this process is known as place and route. It can also take the form of an interactive process that is guided by a designer. This is called custom layout.

Verification

Verification tools examine either the logical or physical representation of the chip to determine if the resultant design is connected correctly and will deliver the required performance. There are many processes that can be used here. Physical verification examines the interconnected geometries to ensure their placement obeys the manufacturing requirements of the fab. These requirements have become very complex and can include far more than 10,000 rules. Verification can also take the form of comparing the implemented circuit to the original description to ensure it faithfully reflects the required function. Layout vs. schematic, or LVS, is an example of this process. Functional verification of a chip can also use simulation technology to compare actual behavior to expected behavior. These approaches are limited by the completeness of the input stimulus provided. Another approach is to verify the behavior of the circuit algorithmically, without the need for input stimulus. This approach is called equivalence checking and is a part of a discipline known as formal verification.

EDA began as a captive capability. Before EDA was a market segment, large, vertically integrated OEMs operated captive chip design and manufacturing capabilities. These organizations employed large teams of software engineers to develop the required tools to automate the design, implementation, and verification of the chips that were manufactured. All chip production in this case was used by the OEMs to include in their own products.

Bell Laboratories, Texas Instruments, Intel, RCA, General Electric, Sony, and Sharp are examples of these companies. The birth of commercial EDA tools essentially happened in three phases.

The first phase began in the 1960s and saw commercial availability of computer-assisted interactive graphics design systems. These systems targeted multiple markets, including cartography, mechanical, and architectural design. These systems also found use for interactive design of integrated circuit layouts. The three primary companies leading this phase were Applicon, Calma, and Computervision. It is interesting to note that in these early days Calma developed a format to represent IC layouts called GDS, named after its product, Graphic Design System. The GDS II version of this format continued to be used as the de-facto format to communicate IC layout information for decades. This phase of the industry was known as CAD/CAM (computer-aided design/computer-aided manufacturing).

The second phase of EDA began in the early 1980s. Something rather significant happened during this time ¨C the commercial application-specific integrated circuit, or ASIC, industry was also born. With the emergence of the ASIC industry, the custom chips that were previously reserved for the very large system OEMs were now within reach of many more design teams. This began the semiconductor revolution that continues today. Early ASIC companies include LSI Logic and VLSI Technology. With this new market, the need for tools to automate the simulation, design, and verification of chips became far more widespread. This development spawned many new companies to serve the need. A lot of the internal, captive teams at the large OEMs found new, exciting, and lucrative work in this new market and so the commercial EDA industry began to grow.

During this phase, the primary focus was on software and some special-purpose hardware to capture the description of a design and simulate it. The three primary companies leading this phase were Daisy Systems, Mentor Graphics, and Valid Logic. This phase was known as CAE (computer-aided engineering).

In the latter part of the 1980s, the EDA industry began to mature as its third phase began. Point-tool companies were replaced with broad-line suppliers of multiple software and hardware products aimed at automating a larger portion of the IC design process. The three primary companies leading this phase were ²ÝÁñÉçÇø, Cadence, and Mentor (now Siemens EDA). This phase saw the birth of the term EDA (electronic design automation). Today, many still identify with this phase of the industry. The three leading companies remain the same.

With the dramatic expansion of semiconductor technology, there is a movement toward a need for a larger platform of tools and technologies which may signal the next phase of the industry¡¯s development.

Semiconductor chips are incredibly complex. State-of-the-art devices can contain over one billion circuit elements. All of these elements can interact with each other in subtle ways, and variation in the manufacturing process can introduce more subtle interactions and changes in behavior.

There is simply no way to manage this level of complexity without sophisticated automation, and EDA provides this critical technology. Without it, it would be impossible to design and manufacture today¡¯s semiconductor devices.

It is also worth noting that the cost of an error in a manufactured chip can be catastrophic. Chips errors cannot be ¡°patched.¡± The entire chip must be re-designed and re-manufactured. The time and cost of this process is often too long and too expensive, resulting in a failure of the entire project. So, the complexity to design chips is high and the need to do it flawlessly is also required.

Without EDA tools, these challenges cannot be met.