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For decades, Moore¡¯s law enabled semiconductor companies to double the number of transistors in an integrated circuit (IC) every two years. As Moore¡¯s law slows, device scaling for monolithic systems-on-chip (SoCs) is noticeably less while the cost of newer, more complex process nodes continues to steadily increase. However, the demand for faster, better, and smarter silicon is only growing as the exploding impact of ¡°Smart Everything¡± and ubiquitous artificial intelligence (AI) drive a massive push for faster speeds and ever-more transistors. We call this intersection of Moore¡¯s law scale complexity with new systemic complexity demands the SysMoore era.

Aart de Geus, ²ÝÁñÉçÇø chair and chief executive officer, recently observed that semiconductor companies are revolutionizing both architectural function and form with new multi-die systems to help meet market demand. Indeed, disaggregating a large monolithic chip design into smaller, proven dies results in higher yields, lower silicon costs over time, and more customizable SKUs. de Geus, who penned the opening chapter of a new ²ÝÁñÉçÇø industry insight report titled ¡°How Quickly Will Multi-Die Systems Change Semiconductor Design?¡± notes that cross-industry collaboration has seen chip designers significantly increase connectivity density while reducing energy switching (per bit). The report also includes insights on multi-die systems from Ansys, Arm, Bosch, Google, Intel, and Samsung.

Accelerating Multi-Die System Adoption with 2.5D and 3D Packaging

As traditional Moore¡¯s law scaling approaches its physical limits, Ansys sees the quest for higher electronic system densities transitioning to multi-die systems with the help of 2.5D and 3D packaging. However, the company emphasizes that successful adoption of multi-die systems hinges on overcoming three challenges: multi-scale, multi-physics, and multi-organizational coordination.

¡°Advanced multi-die systems condense three design scales into one design challenge that crosses six orders of magnitude, from nanometer IC design, through millimeter package design, to centimeter 3D-IC systems,¡± states Ansys. ¡°These solutions are divided into three tool suites (IC, systems, and packaging) that need to be integrated into a single solution.¡±

Ansys says the potential for more capable multi-die systems with higher yields is already positively impacting suppliers of high-performance computing (HPC) processors and graphics, as well as AI and machine learning (ML) enablement at the cloud edge.

Arm expresses similar sentiments, noting that multi-die systems composed of co-packaged chiplets will become widespread across the industry. ¡°Companies will be able to amortize their hardware and software engineering investment by reusing chiplets for multiple products,¡± the company says. ¡°Complex systems will be cleanly partitioned, reducing risk, cost, and time to market.¡±

According to Samsung Electronics, both 2.5D and 3D packaging technologies such as Samsung¡¯s I-Cube 2.xD and X-Cube 3D IC empower device manufacturers to pursue new product designs based on multi-die systems. ¡°Breakthroughs in AI, 5G, autonomous vehicles, and metaverse tech promise to reshape the way we live¡ªbut delivering the function and performance needed to power those advancements on a single chip is becoming more complex and less cost-effective,¡± explains Samsung. ¡°Combining the power and diversity of today¡¯s chips in a unified system brings new products within reach.¡±

Intel notes that advanced packaging is already playing a crucial role in enabling multi-die systems. ¡°Heterogeneous integration using advanced 2.5 and 3D packaging technologies, like EMIB and Foveros, offers an attractive path to architecting products by combining chiplets from various sources, designed on disparate silicon nodes,¡± the company states. ¡°This mix-and-match capability unlocks the ability to optimize for unique functionality, performance, and cost while enabling reuse and modularity.¡±

Expectations for the Future of Multi-Die Systems

Ghazi sees a flood of high-end multi-die systems spanning a wide range of markets by the 2030s. ¡°I say this because of the rapid progress I see, not only in ²ÝÁñÉçÇø¡¯ engineering labs but also the billions of dollars of secure investment going into multi-die systems from across public and private sources.¡±

Specific examples of multi-die system innovations include fusing architectural analysis and implementation as part of multi-die system flows, as well as the addition of AI for a step-function increase in productivity and quality of results. ¡°Even now, our customers and partners are designing products that appeared completely out of reach just a few years ago,¡± says Ghazi.

As Ghazi points out, more than 95% of advanced chips today are built using ²ÝÁñÉçÇø technology. ¡°We¡¯re tracking over 100 designs today, with an uptick of 20% over the last six months,¡± adds Ghazi. ¡°That tells me this is a design direction which is maturing very fast indeed.¡±

Learn More About Multi-Die Systems

²ÝÁñÉçÇø is committed to working with ecosystem partners as we usher in an innovative era of multi-die systems. We can¡¯t wait to see what the semiconductor industry accomplishes next with our AI-driven EDA tools, IP products, and deep system design expertise.

Get an industry-wide look at the accelerated adoption of multi-die systems. Access your copy of the new ²ÝÁñÉçÇø industry insight report here.