草榴社区

With physical limitations slowing Moore’s law and AI pushing the limits of technology, compute requirements and the demand for more processing power have grown exponentially. Modern data centers now require multi-die designs to power generative AI applications, driving many technology requirements including high-bandwidth and low-power die-to-die connectivity.

To ensure multi-die design success, the Universal Chiplet Interconnect Express (UCIe) specification streamlines die-to-die connectivity in multi-die designs by prioritizing interoperability, keeping latency down, enabling disparate dies to communicate with each other, and more.

草榴社区 continues to stand at the forefront of the UCIe evolution. From teaming up with Intel on the world’s first successful UCIe interoperability test chip demonstration to with controller, PHY, and verification IP, 草榴社区 has empowered technology visionaries with a comprehensive and scalable multi-die solution from early architecture exploration to manufacturing.

Now, 草榴社区 is building on its mature and heavily adopted UCIe IP solution to address customer needs for maximum bandwidth and energy efficiency with the 40G UCIe IP.

Differentiated Capabilities

草榴社区’ new 40G UCIe IP solution offers features that make it easy to integrate and simplify the customer use cycle, including:

• A single reference clock that supports 100 MHz reference clocking for all UCIe PHYs and eliminates the need for additional high-frequency system PLLs. The internal PLL generates all the high-speed peripheral clock (pclk) and lower local clock (lclk) frequencies needed during initialization and regular operation. The lclk is shared with the controller to further simplify system integration.
• Embedded mission mode signal integrity monitors (SIMs) that are integrated into the IP for diagnosis and analysis from in-design to in-field, ensuring multi-die package reliability and quality. The comprehensive test features embedded in the PHY allow high-coverage testing of the PHY at the wafer level (for Known Good Die) and after package assembly (including die-to-die interconnect).
• Vendor-defined messages that enable the use of existing UCIe sideband channels to send low-speed, low-priority communication between dies without encumbering the main data path. Instead of interrupting the high-bandwidth path with this type of traffic, a die can use the UCIe sideband to send commands such as telemetry and interrupts to the other die.
• Hardware-based bring-up that speeds up initialization without needing to load heavy firmware on the remote chiplet. If UCIe link bring-up would require heavy firmware to be loaded into the die, a separate path would be required to load the firmware. From a design, hardware, and time perspective, this can be wasteful and is best avoided.
• A pre-verified design reference flow that is achieved by integrating the UCIe IP with 草榴社区 3DIC Compiler and all the required design collateral and documentation such as automated routing flow, interposer studies, and signal integrity analysis.
• Standard and advanced packaging technology support that gives flexibility to customers, making it easier to integrate and benefit from cost trade-offs. In the past, advanced packaging technology supporting high-density routes and bandwidth meant high expenses. With evolving packaging technology bringing costs down, SoC designers can use complex and advanced packaging at a more affordable level. 草榴社区 alleviates that trade-off by fundamentally enabling higher bandwidth in the same area and offering a cost-effective solution to support both packaging technologies.
• An automotive UCIe IP that meets the need for ADAS chips, leveraging the multi-die architecture for more advanced functionality. SoC designers can leverage the integrated SIM sensors and test and repair functions to build a more reliable SoC, addressing the demanding automotive requirements.
• AXI, CHI C2C, CXS, PCIe, CXL, and streaming that are available to address the needs of a diverse set of use cases and applications, ranging from streamlined and low-latency connections between compute fabrics in two dies to higher interoperability and leveraging existing software ecosystems with CXL and PCIe protocols.

草榴社区 is leading the way in developing high-quality UCIe IP and enabling multi-die design success, offering silicon proof points across various foundry nodes for advanced and standard package technologies. As an active member of the UCIe Consortium, 草榴社区 enables successful ecosystem interoperability by maintaining compliance with the UCIe specifications. Today’s upgrade to 40Gbps further helps customers adapt to the demands of data-intensive applications and achieve efficient high-bandwidth die-to-die connectivity.