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UCIe 2.0 - Enabling Interoperability

While the UCIe 1.1 specification revision focused on key extensions for multi-vendor heterogenous systems, UCIe 2.0 is sowing seeds to define a chiplet interoperability ecosystem stack with a ¡°System Architecture¡± definition, introducing provisioning manageability of System-in-Package (SiP).

Let¡¯s explore the new features in UCIe 2.0. 

Management Transport Protocol (MTP)

MTP enables communication between management entities within a SiP management network. Management entities on this network generate and receive UCIe management transport packets, which traverse the network without modification. UCIe Memory Access protocol (UMAP) enables read and write access to memory associated with management entities with ability for access control.

UCIe Debug and Test Architecture (UDA)

UDA is architected for chiplet-level and SiP-level testing and debug. UDA uses functional sideband and/or mainband link and a functional management network for test and debug purposes.

UCIe-S Sideband only (SO) port

SO port is permitted for test/manageability purpose in a standard package. It is meant as an option for a low-speed test port that one can use at TestChip level.

x8, x4 (degraded) link width support for standard package

Capability for x8 (degraded x4) pin module is enabled for standard packages, whereas version 1.1 only supported x16 and x64 physical layer interfaces.

UCIe 3D packaging

3D packaging techniques enable chiplets to be stacked vertically. This method not only boosts performance and reduces latency but also enhances power efficiency, addressing the crucial needs of modern semiconductor designs. By adhering to UCIe standards, 3D packaging enables more compact, high-performance chip designs that can meet the demands of future applications.

In addition to Interoperability, UCIe 2.0 is paving way for defining scalable verification and validation platforms for chiplet designs.

²ÝÁñÉçÇø UCIe End-to-End Verification and Validation ²ÝÁñÉçÇø

²ÝÁñÉçÇø is a contributing member to the UCIe specification committee and is working closely with industry leaders to support features and use cases for the UCIe 2.0 specification in ²ÝÁñÉçÇø Verification IP (VIP) for UCIe 2.0.

²ÝÁñÉçÇø¡¯ complete UCIe IP solution includes controller, PHY, and VIP. ²ÝÁñÉçÇø UCIe controller and PHY IP solutions enable robust and reliable die-to-die links with testability features for known good dies. The IP, operating at maximum data rates, supports standard and advanced packaging technologies and has achieve multiple silicon successes across foundry process and packaging technologies.

²ÝÁñÉçÇø UCIe 2.0 VIP, functional test suites, and protocol solutions for hardware-assisted verification platforms, ZeBu, and HAPS, leverage close collaboration with ²ÝÁñÉçÇø¡¯ industry leading IP portfolio to enable the highest quality verification and validation collateral for our customers.

²ÝÁñÉçÇø silicon proven IPs are verified using independently developed ²ÝÁñÉçÇø VIPs, providing companies with an industry leading UCIe solution. ²ÝÁñÉçÇø SoC verification kit solutions provide ready to go IP bring-up and sanity setup with IP-VIP or IP-²ÝÁñÉçÇø integrations and collaterals, saving at least 50% of time and resources spent in bringing IP up in the SoC Verification environment. With pre-verified components and ready-to-use testbenches ²ÝÁñÉçÇø VIP accelerates the development cycle, reducing time-to-market.

Because the target usage for UCIe is die-to-die interconnects, the payload that the chiplet RTL requires demands faster hardware-based pre-silicon solutions. ²ÝÁñÉçÇø transactors based on ²ÝÁñÉçÇø IP enable fast verification hardware solutions including ²ÝÁñÉçÇø ZeBu? emulation systems and ²ÝÁñÉçÇø HAPS? prototyping systems for validation use-cases.

²ÝÁñÉçÇø protocol verification solutions are natively integrated with the ²ÝÁñÉçÇø Verification Family of products, including ²ÝÁñÉçÇø Verdi? debug and regression management and automation with ²ÝÁñÉçÇø VC Execution Manager.