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Highlights

? Native SystemVerilog/UVM test bench
? Runs natively on all major simulators
? Runtime JEDEC and vendor part selection
? Protocol and timing checks
? Built-in coverage model
? Error injection and timing exceptions
? Verdi protocol-aware debug
? Trace files and debug ports
? Configuration creator GUI

Key Features

? Supports ToggleNAND 2.0 and ToggleNAND 3.0
? Discovery and Initialization
? All basic operation commands
? All extended operation commands
? All interleaving operation commands
? Advanced Configuration: Powerful runtime
constrained random configuration
? Support run time frequency change
? Passive monitor support
? Access to internal states of the model
? Analysis port for scoreboarding
? Configurable number of
    – Targets
    – LUNs per Target
    – Blocks per LUN
    – Pages per Block
    – Bytes per Page