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• DDR5 DRAM and 3DS  JEDEC rev 1.90
• UDIMM
• RDIMM (RCD03 rev 1.0)
• LRDIMM (DB01 rev 1.0)
• All speed bins
• All densities (8Gb to 32Gb)
• All DRAM data widths (4, 8, 16)
• All commands, and burst sizes (BC8/BL32 and on the fly BL)
• Sequential and wrap addressing
• SDR/DDR modes
• Clock stop/frequency change
• PDA, MPSM and 2N mode
• CA parity and ECC
• Trainings (CS, CA, read training pattern, read preamble training, write leveling)
• All mode registers
• On die termination (ODT)
• PPR, DFE, CT Mode
• Partial write, write pattern
• Refresh schedule monitoring, configurable refresh rates, refresh management (RFM)
• DQS interval oscillator

RESET and Initialization Procedure

Skip and fast initialization to speed up simulation

All commands

• MRW, MRR, MPC, RD, WR, ACTIVE, Precharge,
• PDE, PDX, SRE, SRX, ZQ calibration and other commands

All mode registers

• WL/RL
• Preamble/Postamble and other fields

Decision feedback equalization, and loopback

CRC, On-die ECC, DQS Interval oscillator

Trainings

• CS, CA, read training pattern, read preamble training, write leveling
• RCD, DCA and DCS, CA Vref, DQ Vref (2D)

• Up to 2 rank, dual channel
• DDR and SDR modes
• Parity, power down, self refresh, and all DRAM commands
• RCD registers, and BCOM bus
• Output inversion and mirroring, transparent mode

• Callbacks for error generation and commands tracking
• Access to internal states of the model
• Static/dynamic reconfiguration for timing and configuration settings
• Clock jitter (partial)
• 2D Vref DQ modeling to mimic real world eye
• User configurable logical addressing
• Pre buffer and post buffer modeling to enable real world trainings

• Tested against vendor models
• Built-in protocol and timing checks
• Functional coverage model and verification plan
• Analysis port for score-boarding
• ²ÝÁñÉçÇø Verdi Protocol Analyzer and Performance Analyzer