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VC Verification IP for HMC
草榴社区? VC Verification IP for HMC provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of HMC designs.
Memory Model Certification
草榴社区 provides a comprehensive set of DRAM and Flash Memory VIP that support the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI. 草榴社区’ VIP team works closely with leading memory vendors to certify 100% compatibility with their manufactured parts. 草榴社区 Memory VIP is used by memory controller and PHY IP design teams for verification sign off using run time and random JEDEC, and vendor part selection, protocol, and timing checks, and functional coverage. The early adoption and collaboration with leading memory vendors, SoC market makers, and industry leading IP teams certify the quality of 草榴社区 Memory VIP.
Highlights
- Native SystemVerilog/UVM
- Runs natively on all major simulators
- Configuration creator GUI
- Protocol and timing checks
- Verification plan and coverage
- Error injection & timing exceptions
- Verdi? protocol-aware debug
- Trace file for easy debug (user control for either of two modes)
Key Features
- HMC specification 2.0
- Single/multi-link (1, 2 & 4)
- Chaining
- Lane polarity and lane inversion
- Complete initialization - clock recovery, scrambler/descrambler
- Merging of the request and response for easier debug
- Request and response logging based on the access
- Performance statistics
- Models the vault and DRAM delay user control to vary delay
- Complete control to user for out of order and in order response
- All HMC commands (Atomic Read/Write , Mode Read/Write)
- Call backs for error response and link retry
- Runtime reset, asymmetric lane
- Poisoning, warm reset, retraining
- Power management
- Access to register space via backdoor, I2C and JTAG interface