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Verification IP for DDR4
草榴社区 Verification IP (VIP) for the JEDEC DDR4 memory protocol specification provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification convergence on DDR4 based designs. VIP DDR4 is integrated with Protocol Analyzer, a protocol-centric debug environment that gives users an easy to understand, view of memory operations along with a consolidated view of entire address space of Memory. VIP DDR4 is written entirely in SystemVerilog to run natively on any simulator. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage and example tests.
Memory Model Certification
草榴社区 provides a comprehensive set of DRAM and Flash Memory VIP that support the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI. 草榴社区’ VIP team works closely with leading memory vendors to certify 100% compatibility with their manufactured parts. 草榴社区 Memory VIP is used by memory controller and PHY IP design teams for verification sign off using run time and random JEDEC, and vendor part selection, protocol, and timing checks, and functional coverage. The early adoption and collaboration with leading memory vendors, SoC market makers, and industry leading IP teams certify the quality of 草榴社区 Memory VIP.
Highlights
- Native SystemVerilog/UVM/OVM/VMM
- Runs natively on all major simulators
- Runtime JEDEC and vendor part selection
- Verification plan and coverage
- Built-in protocol and timing checks
- Verdi protocol-aware debug and performance analyzer
- Overriding timing parameters
- Backdoor memory access
- Bypass/fast initialization
- Error injection & exceptions
- Trace files and debug ports
- Configuration creator GUI
- Configurable refresh rates
- Delay modeling: Fly by Delay, Trace Delays, Pre- and Post-buffer delays
Key Features
- JESD79-4D JEDEC DDR4 standard
- DDR4 3DS specification Rev 1.0
- MRAM support
- UDIMM, SODIMM, RDIMM, LRDIMM
- Write leveling, GearDown mode training, per DRAM addressability, jitter support
- Temperature controlled refresh, Data Bus Inversion (DBI) and max power savings mode
- Bank group, fine granularity refresh and self refresh break off
- Write CRC, CA parity and multipurpose registers
- Address mirroring
- DFI monitor
