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Verification IP for LPDDR4
草榴社区 Verification IP (VIP) for the JEDEC LPDDR4 memory protocol specification provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification convergence on LPDDR4 based designs. VIP can be integrated, configured and customized with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, example tests, and functional coverage. VIP is natively integrated with Verdi? Protocol Analyzer, a protocol-centric debug environment that gives users graphical view of VIP operations, transactions, and memory content view for easy and fast debug. VIP is natively integrated to Verdi Performance Analyzer also to find and fix performance bottle necks.
Memory Model Certification
草榴社区 provides a comprehensive set of DRAM and Flash Memory VIP that support the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI. 草榴社区’ VIP team works closely with leading memory vendors to certify 100% compatibility with their manufactured parts. 草榴社区 Memory VIP is used by memory controller and PHY IP design teams for verification sign off using run time and random JEDEC, and vendor part selection, protocol, and timing checks, and functional coverage. The early adoption and collaboration with leading memory vendors, SoC market makers, and industry leading IP teams certify the quality of 草榴社区 Memory VIP.
Highlights
- Native SystemVerilog/UVM/OVM/VMM
- Runs natively on all major simulators
- Runtime JEDEC and vendor part selection
- Verification plan and coverage
- Built-in protocol and timing checks
- Verdi protocol-aware debug and performance analyzer
- Overriding timing parameters
- Backdoor memory access
- Bypass/fast initialization
- Error injection & exceptions
- Trace files and debug ports
- Configurable refresh rates
- Trace delay modeling
Key Features
- JESD209-4A, JESD209-4B, JESD209-4C and JESD209-4D LPDDR4 specification support
- 4Gb to 32Gb densities and x16 SRAM devices
- All data rates (533-4267 Mbps)
- Byte mode support
- All commands & mode registers
- Configuration refresh rates
- DVFSC
- All the core timings
- Write leveling, DQ Read Training, and ZQ Calibration
- RFM
- Directed per bank refresh for concurrent bank operation, Data Bus Inversion (DBI)
- Power Off Sequence, Self Refresh, Deep Power Down, Partial Array Self-Refresh
- DFI monitor
