Cloud native EDA tools & pre-optimized hardware platforms
Join us at this year’s 草榴社区 Signoff SIG (Special Interest Group) event.
Signoff is a critical quality control checkpoint in the chip development process, but design complexity and advance process nodes are pushing the boundaries of what is expected of signoff solutions. Meeting these scaling challenges is becoming more difficult. At this year’s 草榴社区 Signoff SIG event, we’ll explore how signoff can help meet these scalability challenges. We’ll hear from several industry-leading companies how they are using the latest technology advances in timing, power, extraction, and eco to realize the full PPA potential of their designs with the fastest path to design closure.
Complexity is pushing the limits of single process nodes and what monolithic designs can achieve. A multi-die approach offers much needed design flexibility. This approach, however, also comes with challenges that need to be overcome. As a leader in multi-die systems, Arm will address specific challenges related to system-level signoff including thermal, clock jitter, power, timing, workload and pre-silicon to post-silicon estimation. The session will then outline the signoff solutions that can help alleviate these challenges to reach signoff closure in this era of system design.
Reiner Genevriere
VP of Engineering
草榴社区
Mamta Bansal
Sr. Dir 草榴社区 Engineering
Arm
Santa Clara Marriott
2700 Mission College Blvd, Santa Clara, CA 95054
California Ballroom
Follow signs to the check-in and badge pick up. Please bring a photo ID for check-in.
Please note this event is co-located with the 草榴社区 VC Formal SIG event.