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Ensuring functional safety and cybersecurity in automotive applications is a challenging task. In this presentation, we will provide an overview of adhering to ISO 26262 for functional safety and ISO/SAE 21434 for cybersecurity, and then delve deeper into the implementation of these standards in automotive SoCs using ARC-V processors. In addition, we¡¯ll cover unique safety mechanisms integrated into ARC-V and NPX processors and how they address potential risks and vulnerabilities. Finally, we¡¯ll discuss the ²ÝÁñÉçÇø tools and software solutions designed to facilitate compliance with these standards, ultimately aiming to provide a robust framework for developing reliable and secure automotive SoCs.

RISC-V provides an architectural framework to address varying computational needs, ranging from the smallest embedded devices to datacenters. While a clear trend exists to use RISC-V for smaller control applications, larger scale adoption for complex SoCs addressing integrity needs driven by new automotive E/E architectures implies changes and challenges. The talk will outline these trends, considering multidimensional requirements with a dedicated focus on dependability.

DSP applications like IoT, radar, vision, sensor fusion, etc. pose diverse requirements on DSP processor IP for enabling efficient implementations. A great variety of algorithms and data types is to be supported for a wide range of data throughputs, including combinations of DSP and AI/ML. There are a wide range of architectural options for DSP workloads, each with their pros and cons. In this presentation, we will provide an overview of the ²ÝÁñÉçÇø DSP Processor IP portfolio, covering the role of RISC-V ISA vector extensions, when to consider specialized DSP instructions and accelerators, the tradeoffs vs. VLIW architectures, and the importance of the load/store capabilities.

Pre-silicon software development and code optimization for performance and density are critical activities for releasing SoCs that meet schedule and spec requirements. Early and accurate performance modeling of highly configurable processors is key to making informed SoC architecture decisions, and taking advantage of RISC-V ISA extensibility requires tightly integrated hardware and software tools. ?This session provides an overview of the broad set of software development offerings available for ARC-V and ARC NPX NPU processors, including optimized compilers, simulators and models for performance modeling and virtual prototyping. ?A tool that simplifies the creation and programming of custom instructions will also be covered.

Electronic and electrical architectures are evolving towards central computing in the automotive market. The centralized architecture provides the opportunity to combine applications such as infotainment and ADAS systems. The combination of in-cabin applications such as driver monitoring with ADAS functions allows the sharing of resources which can result in lowered costs. The ²ÝÁñÉçÇø ARC AI IP integrated into SiEngine's SE1000 SoC supports the central computing trend by executing high-performance AI processing for both in-cabin and complex ADAS algorithms. This talk will discuss the central computing use of AI to combine infotainment and ADAS systems into one chip. This talk will cover the critical role AI plays in the combined solution and how partnerships ¨C like the integration of ²ÝÁñÉçÇø¡¯s AI IP into SiEngine¡¯s SE1000 ¨C can speed time to market.

Many market segments increasingly demand distribution of compute and decision-making functions over a wide array of general purpose and specialized SoC blocks such as application and real-time processors, safety and security monitors, vector DSPs, AI engines, fixed function accelerators and even IO subsystems. Conversely, safety and security standards have introduced isolation requirements limiting the flexibility of temporal and physical allocation of software functions. A holistic resource virtualization strategy implemented across SoC blocks and supported by corresponding software stacks is critical to hitting targets for development scalability, resource utilization and PPA efficiency. This session shares the concept of virtualization design principles leveraging ²ÝÁñÉçÇø Processor IP components in developing next generation SoCs.

Efficiently porting applications to RISC-V relies on several key technical considerations and tools to ensure optimized code for the RISC-V architecture. This session summarizes a structured approach for migrating code to ²ÝÁñÉçÇø ARC-V processors, and includes considerations of total cost of software ownership during and after the migration. Topics include: identifying pivotal architectural differences, compiler insulation, ABI gotchas, custom instructions and intrinsics, and the role of development tools and vendor support.

In this talk, we explore the emerging trends in generative AI for edge devices and the role of transformer-based neural networks at their core. We investigate the distinct attributes of transformers and how they¡¯re advantages over conventional convolutional neural networks (CNNs) enabled Generative AI. The talk discusses key requirements for the latest Neural Processing Units (NPU) to support Transformers and Generative AI constructs to support edge device applications. We use transformer-based vision models, text-to-image, and large language model generative AI examples to illustrate the requirements for efficient mapping onto an NPU.