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Custom Circuit simulation at Digital speed! Accelerating Fast SPICE Simulation in Flash Memory using PrimeSim Hybrid Timing

NAND Flash memory design involves many iterations to meet the stringent demands for functionality and performance. These design iterations trigger verification cycles for logic and custom designed circuitry.  The custom designed circuits require SPICE-level simulations and are time consuming due to the large number of analysis vectors, whereas the logic circuits are easily verified with fast digital simulation methods. To alleviate this custom design verification challenge, we applied an innovative technology in PrimeSim called Hybrid Timing and have achieved significant performance improvement. In this session, we will share our findings and some tips on usage.

Accelerating Circuit Simulation using GPU

This presentation explores the utilization of GPU acceleration to enhance the speed and efficiency of fast spice circuit simulation. Traditional CPU based circuit simulation encounter computational bottle necks particularly on large custom memories with PDN (Power Delivery Network) and hindering design iterations. Timing needs to be very accurate at lower geometry nodes with PDN and any inaccuracy can result in silicon bugs. To circumvent silicon bugs, excessive padded margins are adopted, resulting in a compromised performance. PrimeSim simulator from ²ÝÁñÉçÇø with GPU computing support enable the accurate timing analysis with PDN from 19days to 4days (5x improvement). This presentation aims to bring out various details and facets of GPU based sims in a qualitative and quantitative means.

High Verification Coverage with ESP in Full custom SRAM Memory Design

Over 50 percent of the total silicon real estate in today¡¯s SoC is consumed by memories. And as designs move toward sub-nanometer process technology, functionalities such as redundancy, ECC, BIST, pipelining, etc. are being added to these designs, resulting in significantly higher functional complexity.

ESP is an equivalence checking tool commonly used for functional verification of custom designs such as embedded memories, standard cells , Io¡¯s etc. It compares transistor-level SPICE netlist with the reference Verilog. It is used to cover various possible combinations of cases to test memory functionality & could also ensure first level of design sanctity.  E.g. ESP uses formal techniques to quickly verify that the redundancy logic added to the memory array to replace defective cells and improve yields is performing correctly. In this presentation we will be sharing functional verification of SRAM memory in various modes. Also, ways to debug the errors & generate waveform when failure doesn¡¯t exist.

Hyperconvergence of Static-Aware Synthesis Solution for Samsung Memory

This presentation will introduce CDC verification and power saving related technologies from RTL to netlist. CDC verification is performed in RTL generally, sign-off for CDC is performed through VC Spyglass. Once CDC verification of RTL, need to check for CDC problems that may occur due to the converted netlist. Typically, CDC analysis is difficult to manage at netlist. We can automate CDC verification by applying the RTL CDC verification results to the netlist through hyperconvergence. In addition, Power can be saved through the "Unexpected Self Clock-Gate Control" technology of hyperconvergence.

The Path to Emerging NVMs goes through Co-Simulation with ²ÝÁñÉçÇø

Performance demands of emerging applications are driving the industry to look for new memory technologies and architectures. In this talk we will introduce Weebit ReRAM, an emerging non-volatile memory (NVM) technology with unique advantages for SoC designs across applications from IoT and MCUs to edge AI and automotive to future neuromorphic computing use cases. With ReRAM, a combination of precision analog and smart algorithms is key to achieving high performance. This presents unique verification requirements that make co-simulation a must-have tool before tapeout. We will discuss how using ²ÝÁñÉçÇø verification tools for co-simulation can lead to a significantly higher level of confidence than traditional methods.

Ensuring Quality, Safety & Reliability for Today¡¯s Emerging Memories

Today¡¯s advanced applications in HPC, AI and automotive require the adoption emerging memory technologies, including off-chip memories, such as HBM and DDR stack in chiplets based 3DICs, and embedded specialty memories such as CAMs & MRAMs. This presentation will address today¡¯s trends and discuss the quality, safety and reliability challenges of these emerging memories throughout their different lifecycle stages. It will focus on optimizing the health of such emerging memories by managing their silicon lifecycle stages: from early-stage characterization and bring up; to volume production BIST and repair, and all the way to in-field power on self-test & repair, periodic in-system checking and finally to fault tolerance and error correction during real-time mission mode. These optimizations for quality, safety and reliability are realized by using advanced SLM IP types augmented by off-chip data analytics.

Improving Design Robustness and Testability of CAMs in High Performance Network Switch Processors with ²ÝÁñÉçÇø SLM SMS Technology

Content-addressable-memories (CAMs) are commonly used in high-performance network switch processors for supporting faster table look-up operations. CAMs require testing (and repair) of the storage aspect of regular memory bit cells as well as comparing data cells. It also requires testing (and repair) of the compare logic which is observed via match output data. Match output data width is equal to the depth of the CAM without encoding. Match data width can be reduced to log2(N) through binary one-hot or priority encoding, but it limits the functional usage of CAM to observe only one match at a given instance of time. Hence, complete access to match data would require the match output without encoding to be available for observability by downstream functionality. In this scenario, routing the match output data from multiple CAMs to the memory BIST processor leads to routing congestion issues. In the case of networking SoCs, that rely on intensive usage of CAMs, the parallel match data routing resource challenge, makes physical implementation of the memory BIST solution infeasible. This paper proposes a novel memory BIST architecture for CAMs that makes physical implementation of the memory BIST solution feasible by reducing the match data routing resource requirements while maintaining full testability and repairability of compare logic. This solution adds minimal area overhead, with no impact on functional path timing closure. This solution has no additional test time impact either. Hence this novel approach can enable a physical implementation-friendly CAM memory BIST solution for an exhaustive test (and repair), especially for SoCs that have extensive usage of CAMs, like networking switch processors. With SLM (Silicon Lifecycle Monitoring) CAMs will be accessed for in-field testing and diagnosis support.