Cloud native EDA tools & pre-optimized hardware platforms
Industry's best performance efficiency for embedded
The 草榴社区 ARC? EM Family, based on the ARCv2 instruction set architecture (ISA) includes ARC EM4 and EM6, DSP-enhanced EMxD processors, and ASIL compliant EM functional safety processors.
The ultra-compact EM cores feature excellent code density, small size and very low power consumption, making them ideal for power-critical and area-sensitive embedded and deeply embedded applications.
The ARC EM processors are supported by a broad ecosystem of commercial and open-source tools, operating systems and middleware. This includes offerings from leading industry vendors who are members of the ARC Access Program as well as a comprehensive suite of free and open source software available through the embARC.org website.
For embedded and deeply embedded applications where high performance with minimum power consumption is essential
? Performance-efficient RISC cores
? Minimal power and area
? Excellent code density
For embedded applications where DSP performance and low-power consumption are required
? Combined RISC + DSP processors
? Over 150 DSP instructions
? Easy DSP programming support
For DSP-intensive functions such as sensor fusion, voice detection, speech recognition and audio processing
? XY multi-banked memory
? Fixed-point, vector/SIMD DSP support
? Low-power, unified 32x32 MUL/MAC unit
Ultra-compact core for low-power safety critical automotive applications
? Dual-core lockstep processor
? Self-checking safety monitor
? Support for safety levels up to ASIL D
ARC Software Development Platforms:
ARC Development Tools and Software:
Option |
Supported ARC EM Processors |
*This feature comes standard with this processor
ARC processors are optimized to deliver the best PPA efficiency in the industry for embedded SoCs.
ARC processors are highly configurable, allowing designers to optimize the performance, power, and area of each processor instance on their SoC.
ARC Processors EXtension (APEX) technology enables users to customize their processor implementation.