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High-Performance, Mid-Range, and Ultra-Low Power RISC-V Processor IP

草榴社区 ARC-V Processor IP? is based on the open standard RISC-V instruction set architecture (ISA), extending the current ARC portfolio and giving customers access to the growing RISC-V ecosystem. Built on the success of multiple generations of ARC processor IP covering a broad range of processor implementations, including functional safety (FS) versions, the ARC-V portfolio delivers what you need to optimize and differentiate your SoC.

To accelerate software development, the ARC-V processors are supported by the trusted 草榴社区 MetaWare Development Toolkit. In addition, 草榴社区’ extensive portfolio of EDA tools provide an out-of-the-box development and verification environment to help design and fully verify RISC-V-based SoCs.

Key Benefits

scale

Power & Area Efficient

Achieve maximum performance with minimum power and area consumption

configurability

Configurable

Optimize PPA of each processor instance

reliable

Extensible Instruction Set

Make application-specific customizations

speed

Broad Ecosystem

Achieve faster time to market

What's New

ARC-V Processor IP Families

Resources

Quotes from 草榴社区 ARC Customers and Partners

Lauterbach, the world's leading manufacturer of debug and trace tools and long-standing partner of 草榴社区, fully supports 草榴社区' RISC-V-based ARC-V? Processor IP with its TRACE32 tools as a result of close collaboration between the companies' engineering teams. Lauterbach and 草榴社区 are now continuing this close collaboration with joint customers to support them in optimizing and differentiating their chips and helping designers manage the complexity of today's SoCs."

Lauterbach GmbH | Stephan Lauterbach, Founder and CTO

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As the leading provider of system IP we see firsthand the increasing adoption of RISC-V processor IP by our customers, from automotive to consumer electronics to industrial applications. 草榴社区’ ARC-V? Processor IP is a welcome addition to the RISC-V ecosystem, and we look forward to continued collaboration leveraging Arteris’ FlexNoC and Ncore network-on-chip IP to deliver optimized IP solutions and SoC connectivity to mutual customers."

Arteris

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K. Charles Janac, president and CEO

The breadth of the markets we serve requires our designers to have the flexibility to implement the most efficient processor for the job. As a user of 草榴社区 ARC? Processor IP as well as RISC-V IP, among others, we think 草榴社区’ adoption of the RISC-V ISA is a good addition to the choices available in the RISC-V ecosystem."

Synaptics

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Saleel Awsare, Senior Vice President and GM of Enterprise and Mobile

Our PX5 RTOS supports the increasingly popular RISC-V architecture, and we are pleased to see 草榴社区 expand its processor portfolio to include RISC-V compatible processor IP. The PX5 RTOS offers fast and deterministic performance in a small memory footprint, and along with 草榴社区’ ARC-V? Functional Safety Processors, can offer designers an efficient, reliable solution for their safety-critical, real-time systems."

PX5

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Bill Lamie, CEO

TASKING is proud to announce its support for 草榴社区’ ARC-V? Processor IP. Our system-level verification and debugging tools are now available for use with ARC-V IP, whether simulated with the 草榴社区 Virtualizer Development Kit or implemented in an FPGA or silicon. We are working closely with 草榴社区 and their automotive customers to establish a trusted ecosystem for the development of systems that must meet functional safety and cybersecurity standards such as ISO 26262 and ISO 21434."

TASKING

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Gerard Vink, RISC-V Product Line Responsible

As a manufacturer of debug tools, we see the growing importance of making software behavior visible in complex SoCs and the need for a powerful ecosystem to help companies accelerate their release cycles. As a long-standing partner of 草榴社区, PLS has a history of providing high-quality debug tools to 草榴社区 ARC? processor customers and will continue to support the new ARC-V? Processor IP family with the PLS Universal Debug Engine."

PLS

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Jens Braunes, Product Marketing Manager