草榴社区

Debug Options for ARC Cores

Real-time Instruction and Data Tracing for ARCv2 ISA-based Cores

Supports ARC EM, ARC HS, ARC VPX, and ARC EV Processor Cores

The 草榴社区 ARC? Real-Time Trace (RTT) unit is a hardware module that provides a real-time tracing capability that helps trace executed instructions or program flow and data. It provides an added dimension to aid debugging of 草榴社区 ARC processors that are based on the ARCv2 instruction-set architecture (ISA). ARC RTT generates Nexus 5001 class 3-compliant trace messages. It supports real-time instruction and data tracing for all members of the ARC EM, ARC HS, ARC VPX, and ARC EV processor families. ARC RTT is compatible with the ARC MetaWare, the and TRACE32 debuggers.

The ARC RTT supports single- and multi-core ARCv2 implementations, up to a maximum of four processors. The RTT system can be set up in many different configurations, which need to be specified as build-time configurations by including the trace generator in the core and the RTT module at build time. Everything is then automatically handled by the ARChitect tool. ARC RTT can support on- and off-chip memory setups to suit your application tracing needs.

Small Rapid Program Tracing Module Spots Hard-To-Find Bugs

Supports ARC EM, HS, 700 and 600 Cores

草榴社区' Small Real-Time Trace (SmaRT) is a hardware module that can be integrated into any system-on-chip (SoC) within the 草榴社区 ARC configurable architecture. Delivered via the 草榴社区 ARChitect configuration tool as an IP library component, it enables rapid software debug with minimal increase in die size and little power consumption penalty.

SmaRT gives developers the ability to trace program execution precisely in the real system. They can therefore diagnose bugs that are difficult to reproduce in system simulators, or only become apparent when the system is run at full speed.

The system works by recognizing any change of program flow control: the relevant source and destination instruction addresses are then recorded within a stack structure. When the processor is halted, the resultant execution history can be read back by the MetaWare debugger via the SoC's JTAG port: no special interfaces or external hardware are required.

Product Name Supported ARC Processors
ARC Real-Time Trace (RTT) Option ARC EM Family
ARC HS Family
ARC VPX Family
ARC EV Family
ARC Small Real-Time Trace (SmaRT) ARC EM Family
ARC HS Family
ARC 600 Family
ARC 700 Family

草榴社区 ARC Real-Time Trace Unit for ARCv2 Processors Datasheet
草榴社区 ARC Trace Interface Datasheet

Debugging with ARC Real-Time Trace

DesignWare® ARC® Real-time trace allows you to capture trace from an ARC HS core using an Ashling Ultra-XD pod and upload it to the debugger at gigabit Ethernet speeds. Captured trace can be turned into a "replay" database enabling you to debug your program by executing it both forwards and backwards. Watch this video to learn about trace filtering, program profiling from trace, and additional replay features, such as call stack history as well as trace replay for multicore.

Tom Pennello
Principal R&D Engineer, 草榴社区

 

Highlights
Products
Downloads and Documentation
  • Spot Hard-To-Find Bugs
    • The ARC SmaRT and RTT modules record actual instruction flow, locations and makes them available via the MetaWare Debugger. The ability to trace the exact execution path allows engineers to identify and correct the toughest of bugs.
  • Minimal Area and Power Penalty
    • The ARC SmaRT and RTT trace units can be disabled in normal operation, reducing its impact in terms of power consumption to effectively zero. They have a minimal gate count impact on an SoC with small implementations being less than 8.5 K gates. This minimizes area and also power consumption. 草榴社区 SmaRT and RTT trace units utilize the SoC's existing JTAG port, so it requires no additional interface circuitry.
  • Easy To Integrate
    • The ARC SmaRT and RTT are supplied as hardware RTL IP that can be included on-chip by a designer using the 草榴社区 ARChitect processor configurator tool. Using this GUI-based design tool allows them to be easily configured to suit their debugging needs within their SoC. The RTT trace unit supports up to four ARC cores.
  • Easy To Use
    • 草榴社区 SmaRT and RTT are both designed for use in conjunction with the MetaWare Debugger. The debugger can be used to switch tracing on and off as part of normal program execution, by setting a control bit. Trace results can be displayed in an intuitive fashion, along with other program information available to the debugger.
ARC Debug Option for all ARC CoresSTARs Subscribe
ARC SmaRT, optional Real-Time Trace debugSTARs Subscribe
Optional trace module for ARC HS, EM or EV Processors in either Nexus or ARM CoreSight Debug / Trace InfrastructureSTARs Subscribe
Description: ARC Debug Option for all ARC Cores
Name: dwc_arc_debug
Version: 2.1b
ECCN: 3E991/NLR
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation: Contact Us for More Information
Download: arc_debug
Product Code: 4794-0, 7849-0, 7850-0, 8022-0, 8023-0, 8024-0, 8025-0, 8026-0, 8027-0, 8028-0, 8045-0, 8046-0, 9169-0, 9170-0, A279-0, A280-0, A281-0, A282-0, A603-0, A604-0, A605-0, A628-0, A629-0, B140-0, B141-0, C238-0, C239-0, C240-0, C241-0, C242-0, C243-0, C244-0, C245-0, C246-0, C247-0, C248-0, C249-0, C250-0, C251-0, C252-0, C897-0, C898-0, D089-0, E584-0, E756-0, E832-0, E876-0
Description: ARC SmaRT, optional Real-Time Trace debug
Name: dwc_arc_smart
Version: 2.2.2
ECCN: 3E991/NLR
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: arc_ARC_SMART
Product Code: 8034-0
Description: Optional trace module for ARC HS, EM or EV Processors in either Nexus or ARM CoreSight Debug / Trace Infrastructure
Name: dwc_arc_trace_interface_option
Version: 3.60a
ECCN: 3E991/NLR
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: arc_hs47d_processor
Product Code: C340-0