Performance Mode Option for 草榴社区 ARC EM Processors
In a multi-tasking system, multiple processes execute on a single CPU, storing the system state for one process, so the active task can be paused and a different task can be restored and resumed. These tasks do not interfere with each other and appear to be concurrent by the means of context switches that occur in a short period of time.
The 草榴社区 ARC? EM Performance Mode Option provides a coarse-grained multi-tasking architecture featuring a 4-cycle hardware context switch, which allows for higher performance in real-time, low-latency control applications while adding wider memory interface support to improve system I/O performance.
With the performance mode option enabled, the external task controller can choose any task to run next with a context switch based on the Task ID and C-based software development with no need for an RTOS.
In addition, the performance mode option also provides the ability to configure the memory interface to the closely coupled memories (CCM) with 32-, 64- or 128-bit data widths, enhancing the bandwidth and throughput of memory transactions.
ARC EM Multi-tasking Architecture
Performance Option for 草榴社区 ARC EM Processors
- Coarse grained multithreading with 4-cycle hardware context switch
- Save/Restore the context to an external memory using the background copy interface
- Control the behavior of the processor during task switching using the external task switching controller
- 32-/64-/128-bit Direct Memory Interface (DMI)
- Support for DCCM size up to 64KB
- Job Location Address Translation (JLAT) for hardware-based memory mapping
| Description: | Coarse grained multithreading and wider DMI I/F |
| Name: | dwc_arc_em_performance_option |
| Version: | 5.70a |
| ECCN: | 3E991/NLR |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: | |
| Download: | arc_em_processor |
| Product Code: | G753-0 |