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Optimizing PPA for 3D Chips

In its advanced packaging line-up, Samsung Foundry offers options for 2.5D and 3D designs. The foundry¡¯s I-Cube? 2.5D package uses parallel horizontal chip placement for better performance and heat mitigation. Its X-Cube? 3D IC package stacks components to deliver high bandwidth and low power.

The new architectures presented many challenges to traditional design methods, affecting these areas in particular:

• Package and chip co-optimization
• Design turnaround time
• Design rule complexity
• Multi-physics analysis

Having multiple dies integrated into a single advanced package makes it imperative to optimize the package and the chip together. The dies in the system could be from different foundry process nodes and support different functions, such as memory, compute, and high-speed communication. Designing SoC dies targeting advanced packages demands higher effort to accommodate 3D interconnect objects that impose an extra keep-out zone. Floorplanning and optimizing the highly time-critical circuit are also important. Numerous interconnects between dies through bumps must be designed together while two dies are evolving in parallel. It¡¯s common to encounter multiple iterations and refinement steps. Multi-physics effects such as heat dissipation, power, IR drop, and signal integrity must be considered between dies and between the dies and the package. Analysis for static timing, thermal, and power integrity calls for an understanding of these areas within the scope of the entire system. For example, designing the power distribution network and planning sufficient bump and through-silicon vias (TSVs) on multiple dies together, with consideration to quality, carries a substantial impact in power integrity and heat distribution. Meanwhile, the package and these dies, or chiplets, would have their own complex design rules. As a result, turnaround time for a multi-die system can potentially take twice as long as completing a monolithic SoC.

However, with a better understanding of their system, designers can optimize how they stitch together different elements to deliver the best power, performance, and area (PPA) for their targeted applications. Another factor in achieving PPA success is the workflow efficiency and efficacy of the teams involved in the entire design process. In the 2D IC world, it¡¯s fairly straightforward for the implementation team to pass along their completed chip-level design to the packaging team for their contribution. With multi-die systems, however, much more back-and-forth collaboration between the different teams is needed because of the interdependencies. 

Unified Exploration-to-Signoff Platform for Multi-Die Systems

After an evaluation of different solutions on the market, Samsung Foundry found that the ²ÝÁñÉçÇø 3DIC Compiler unified multi-die/package co-design and analysis platform helped overcome key challenges of multi-die system implementation. ¡°With the unified database connected to the ²ÝÁñÉçÇø Digital Design Family, ²ÝÁñÉçÇø 3DIC Compiler, which is qualified for our multi-die system integration process flow down to 2nm and supports our I-Cube and X-Cube technologies, provides a scalable and efficient exploration-to-signoff platform for multi-die systems,¡± said Jun Seomun, principal engineer and project lead, Design Technology Team at Samsung Foundry. ¡°Collaborating with ²ÝÁñÉçÇø to provide a certified multi-die system design reference flow, we¡¯re enabling our mutual customers to realize their PPA and system functionality targets and to do so with high levels of productivity.¡±

Indeed, having a solution that automates design and implementation tasks fuels engineering productivity and enables faster turnaround times, eliminating the manual, error-prone processes that are required when designers attempt to use point tools for these tasks. With the unified database, the Samsung team can efficiently analyze and optimize its 3D package in the scope of entire systems, addressing signal, power, and thermal issues at a system level for better quality of results.

Samsung¡¯s Multi-Die System Implementation Flow with ²ÝÁñÉçÇø 3DIC Compiler, available on the Samsung Foundry 5/4/3nm process, provides:

• A hierarchical physical design flow
• TSV implementation
• Bump implementation
• Interface bump alignment check

²ÝÁñÉçÇø and Samsung Foundry have enjoyed a close collaboration on advanced technologies, including other . For instance, the ²ÝÁñÉçÇø Multi-Die System Solution, of which 3DIC Compiler is an integral component, supports I-Cube and X-Cube silicon stacking and advanced packaging technologies. The two companies have teamed up to develop IP for multi-die systems, including  for Samsung Foundry¡¯s most advanced process technologies.