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If it seems like everyone’s talking about multi-die systems, you’re not mistaken. The semiconductor industry isn’t only talking about them—multi-die systems are already in the market. With compute demands ballooning and Moore’s law waning, integrating multiple heterogeneous dies, or chiplets, into a system in the same package offers a way to meet aggressive power, performance, area (PPA), cost, and time-to-market requirements. Multi-die systems allow designers to accelerate scaling of system functionality at a cost-effective price, reduce risk, and rapidly create new product variants for flexible portfolio management.

But while the multi-die system train left the station a year or two ago, it has really only been chugging along. Until now. The coming year, 2023, looks to be an inflection point as multi-die systems start to make deeper inroads into the mainstream semiconductor world.

Why do we think 2023 is the year for the seismic shift to multi-die systems? The big change is that the broader ecosystem around these architectures is maturing, providing greater opportunities for cost-effectiveness as well as success. Investments in design and verification tools, IP, and manufacturing are converging to help overcome previous barriers, paving the way for adoption of multi-die systems to ramp up. Read on for more insights into what’s on tap for multi-die systems in the coming year.

Maturing Multi-Die System Ecosystem

The ecosystem around multi-die systems is maturing quickly, and this is critical to enabling wider adoption. While chipmakers such as , , , and  already have such designs on the market, other key players in the industry are making serious inroads. One big driver is in tool enablement. While proprietary tooling and scripting requiring manual analysis have been prevalent, there are now a broader range of holistic, unified, and mature tools that ease design, verification, testing, signoff, and silicon lifecycle management functions, hiding the deep complexity from users. Standardized IP for robust and secure die-to-die connectivity is now available, too, to lower integration risks and accelerate the chiplet market.

Another sign of the maturing ecosystem is the activity on the foundry side. There are alliances, flows, and advanced packaging technologies available to support multi-die systems. 草榴社区 is a part of key industry alliances and 草榴社区 3DIC Compiler co-design and co-analysis platform is qualified for key flows and production-proven for advanced packaging technologies. Outsourced semiconductor assembly and test (OSAT) providers are other players in the manufacturing supply chain providing the required technology for multi-die packaging.

Indeed, advances in the packaging landscape are contributing to the multi-die growth. Most notably, silicon interposers, redistribution layer (RDL), and 3D-stacked advanced packaging have provided a significant breakthrough, delivering high integration density and improved power efficiency and performance.

On the standards front, the Universal Chiplet Interconnect Express (UCIe) specification is proving to be a key enabler, and is emerging as standard of choice for die-to-die connectivity for various reasons:

• The specification currently supports 2D, 2.5D, and bridge packages, and support for 3D packages is expected
• It’s the only standard with a complete stack for the die-to-die interface
• And it supports bandwidths of up to 32 Gbps per pin—enough for today’s and future applications

Yet another technology that is seeing a lot of development is silicon photonics, which uses the power of light to transmit and process data and is taking hold in heterogeneous multi-die packages. By delivering energy-efficient bandwidth scaling, photonic ICs integrated into multi-die systems provide an answer to address increasing power and data volume challenges. , a company formed by 草榴社区 and Juniper Networks, provides an open silicon photonics platform with integrated lasers that simplifies the process of integrating silicon photonics into a chip design.