草榴社区 Cloud
Cloud native EDA tools & pre-optimized hardware platforms
Request a Free Trial →
About VC SpyGlass Lint
The VC SpyGlass? linting solution integrates industry-standard best practices with 草榴社区’ extensive experience working with industry-leaders. Lint checks include design reuse compliance checks such as STARC and OpenMORE to enforce a consistent style throughout the design, ease the integration of multi-team and multi-vendor IP, and promote design reuse.
VC SpyGlass Lint uses inbuilt formal techniques to pinpoint deeper functional problems in RTL designs without requiring test benches or assertions. The integrated solution of traditional linting technology with formal technology leverages the comprehensive and widely used lint checks within functional lint flow resulting in noise reduction and improved accuracy of results. The Functional Lint analysis coupled with the increased ease of use results in advanced debugging and interactivity.
Key Benefits
Identify Critical RTL Design Issues
Sophisticated static and dynamic analysis with GuideWare? Methodology
ML-Based Root Cause Analysis
Easier and faster handling of millions of violations
Electrical Rules Check
Integrated comprehensive set of electrical rules check to ensure netlist integrity
Single-Step Inbuilt Formal Flow
For noise reduction
Comprehensive Variety of Rulesets
Design Reuse Compliance Checks: STARC, OpenMORE, ISO 26262 and DO-254 rulesets
Verdi? Integration
Provides a debug environment to enable easy cross-probing
Efficient Rule Execution
Tcl shell for efficient rule execution and design querying
SoC Abstraction Flow
Faster performance and low noise
Features
A multitude of coding styles, structural and electrical design issues can manifest themselves as design bugs and result in design iterations or silicon respins. Other tools may detect design bugs but often at late stages of design implementation, after a significant investment in time and effort has already been made. As design teams become geographically dispersed, consistency and correctness of design intent become a key challenge for chip integration teams. Emphasis on design reuse and IP integration requires that design elements be integrated and meet guidelines for correctness and consistency within a shorter span than necessary.
Resources
Quick Tasks
Support and Training
SolvNetPlus
Explore the 草榴社区 Support Community! Login is required.
SNUG
Erase boundaries and connect with the global community.