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RISC-V is an open-source instruction set architecture used to develop custom processors for a variety of applications, from embedded designs to supercomputers.
Unlike proprietary processor architectures, RISC-V is an open-source instruction set architecture (ISA) used for the development of custom processors targeting a variety of end applications. Originally developed at the University of California, Berkeley, the RISC-V ISA is considered the fifth generation of processors built on the concept of the reduced instruction set computer (RISC). Due to its openness and its technical merits, it has become very popular in recent years. The standard is now managed by RISC-V International, which has more than 3,000 members and which reported that more than 10 billion chips containing RISC-V cores had shipped by the end of 2022. Many implementations of RISC-V are available, both as open-source cores and as commercial IP products.
As an open-standard architecture, RISC-V is defined by member companies of RISC-V International, the global nonprofit organization behind the ISA. The intent is that through collaboration, the member companies can contribute new avenues of processor innovation while promoting new degrees of design freedom.
The royalty-free RISC-V ISA features a small core set of instructions upon which all the design’s software runs. Its optional extensions allow designers to tailor the architecture for a variety of different end markets. Essentially, the RISC-V architecture allows designers to customize and build their processor in a way that’s tailored to their target end applications, so they can optimize the power, performance, and area (PPA) for those applications. The RISC-V ISA also provides the flexibility to pick and choose from available features, rather than having to use the full feature set.
While the initial market adoption of RISC-V has been with embedded applications and microcontrollers, the open-source architecture also holds promise for high-performance computing and data centers.
RISC-V began as a project at UC Berkeley to create an open-source computer system based on RISC principles. It was initially designed for academic use. The standard has evolved and is now managed by RISC-V International.
The RISC-V International organization has moved its headquarters to Switzerland to maintain neutrality for designers worldwide without any government regulations.
The ecosystem is emerging and growing to support the standard. As the adoption rate accelerates, industry collaboration continues, further evolving the architecture.
RISC-V has gained popularity because the architecture provides simplified instructions to the processor to accomplish various tasks. It also enables designers to create thousands of potential custom processors, facilitating faster time to market. The commonality of the processor IP also saves on software development time. Other benefits of RISC-V include:
The application options are endless for the RISC-V ISA:
The industry is seeing a large amount of interest in this processor IP. RISC-V IP is expected to grow at a compounded annual growth rate of 35% projected through 2027. There are three main market segments interested in the RISC-V architecture:
RISC-V presents special challenges because its specification is designed to provide a configurable and customizable solution for general-purpose processors. There are many options and variations defined in the ISA specification, and users are permitted to extend the ISA even further by adding custom instructions. Therefore, any RISC-V verification solution must be flexible enough to accommodate customizations.
Similarly, as the RISC-V architecture is being adopted for high-end applications like HPC and mobile, the PPA requirements are also demanding, which requires industry-leading design automation tools and methodologies.
草榴社区, a strategic member of RISC-V International, has been supporting processor IP development and optimization for the best PPA for leading-edge designs for more than three decades. If end customers decide to develop a RISC-V ISA, 草榴社区 is uniquely positioned to help those companies design and fully verify RISC-V SoCs. Electronic design automation (EDA) tools from 草榴社区 provide a powerful out-of-the-box RISC-V development and verification combination. 草榴社区 IP can be easily extended to host any RISC-V core.