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Description: The presentation introduces GLOBALFOUNDRIES? 22FDX? as the technology and design platform of choice for the next generation of automotive designs. 22FDX? is qualified for Automotive Grade 2 and 1 application profiles. Especially Automotive Grade 1(AG1) requires a specific design methodology composing GFs AG1 PDK components, ²ÝÁñÉçÇø? AG1 foundational IP like standard cell libraries, AG1 margins for reliability and design robustness, and ²ÝÁñÉçÇø? digital implementation tools and flows into a consistent and tape-out proven design platform. The presentation focuses on design guidelines for AG1 reliability (aging), high sigma design and additional margining. The presentation also summarizes the features of GLOBALFOUNDRIES¡¯ digital reference flows using ²ÝÁñÉçÇø? Design Compiler?, IC Compiler? II and IC Validator.

Ulrich Hensel

DMTS Design Enablement, GLOBALFOUNDRIES

Speaker: Ulrich Hensel is driving design methodology topics from the very beginning of GLOBALFOUNDRIES in 2009. He has covered Place and Route technology files and flows, design for manufacturing, digital implementation and sign-off flows, benchmarking, design guidelines, margining, and reliability. He has been focusing on GLOBALFOUNDRIES FDX? technologies including, since 2018, automotive design enablement. Before GLOBALFOUNDRIES was formed out of AMD, Ulrich worked in several digital design and design verification roles contributing to wireless communication, southbridge, northbridge and PCIE designs. He received his Diploma and Doctorate degree in Computer Science from the University of Technology in Dresden.

Description: Demand for real time connectivity in hyperscale data center SoCs is growing significantly due to complicated heterogeneous workloads that require massive parallel processing, thus leading to explosion of machine-to-machine traffic. In addition, as SoCs reach reticle sizes, designers are splitting the SoC into multiple dies that are then assembled in the same package, requiring reliable die-to-die connectivity. This session highlights the different use cases for high-speed SerDes IP and describes the different considerations that go into selecting the optimal 112G/56G Ethernet PHY IP for true long reach performance. This session also explains how designers can leverage SerDes-based PHY for 112G USR/XSR links and parallel-based HBI to meet their multi-chip module design needs.

Manmeet Walia

Senior Product Manager, ²ÝÁñÉçÇø Group, ²ÝÁñÉçÇø

Speaker: Manmeet Walia is a Senior Product Manager for Mixed-Signal PHY IP at ²ÝÁñÉçÇø. He brings more than 18 years of experience in product marketing, product management and system engineering covering ASSP, ASIC, and IP products for broad range of applications. Manmeet holds a Master of Science degree in Electrical Engineering from University of Toledo, and a MBA from San Diego State University.

Manuel Mota

Product Marketing Manager, ²ÝÁñÉçÇø Group, ²ÝÁñÉçÇø

Speaker: Manuel Mota joined ²ÝÁñÉçÇø in 2009 as a Product Marketing Manager and is responsible for the ²ÝÁñÉçÇø Data Converter, High-Speed SerDes, and Bluetooth IP product lines. He brings more than 18 years of technical and marketing experience to his position. Prior to ²ÝÁñÉçÇø, Manuel held product marketing, business development, and IP design positions at MIPS Technologies and Chipidea Microelectronica. Manuel holds a PhD in Electronic Engineering from Lisbon Technical University which he completed while working at CERN (Switzerland) as a Research Fellow. He has authored multiple technical papers and presented in several technical conferences on analog and mixed signal design.

Description: In the fast-growing domain of electric vehicle development, many challenges exist. Range anxiety and cost are adoption barriers, in addition to challenges with hardware and software related to design complexity. It is extremely important to have tools and processes that deliver efficiency throughout the design cycle as well as in the final product. This presentation discusses how a unified virtual prototyping solution, which addresses the multi-discipline needs of system, electro-mechanical, and embedded software domains, can help to ¡°shift left¡± the design phase and accelerate testing efforts. The ¡°shift left¡± practice enables finding defects early in the software development and testing process. 

The presentation includes a case study that looks at early verification requirements with fast, highly abstracted simulations, all the way through to highly refined simulations, and progresses through the design cycle. 

Topics covered include: 

A study of a high-level kilometer range, starting with the electromechanical system. An AUTOSAR application software simulation combined with a refined electromechanical plant simulation for accelerated development. Running a high-fidelity full software stack simulation with highly refined power electronics, serving as a foundation for full system verification.

Kevin Brand

Sr. Staff Applications Engineer, Verification Group, ²ÝÁñÉçÇø

Speaker: Kevin is a Sr. Staff Applications Engineer at ²ÝÁñÉçÇø. He has been in the field of virtual prototyping for 15 years. With a strong focus on automotive, he has been working in R&D and, in more recent years, directly enabling and deploying virtual prototyping solutions at semiconductor, Tier 1, and OEM companies.  

Description: This session describes automotive IP for safety critical ADAS applications. The IP must meet requirements for ASIL target safety integrity levels including compliance to ASIL systematic development flow. Both the safety critical ADAS SoC and IP must go through comprehensive steps to meet automotive-grade standards including ISO 26262 functional safety, AEC Q100 reliability, and ISO 9001 quality management system. Learn more about the automotive IP including ISO 26262 compliant development process to achieve ASIL systematic targets.

Ron DiGiuseppe

Sr. Strategic Marketing Manager, ²ÝÁñÉçÇø Group, ²ÝÁñÉçÇø

Speaker: Ron DiGiuseppe, Senior Strategic Marketing Manager at ²ÝÁñÉçÇø, is responsible for automotive segment marketing for ²ÝÁñÉçÇø IP solutions for ADAS, Functional Safety, Infotainment and MCU applications. Ron brings more than 18 years of semiconductor experience to ²ÝÁñÉçÇø. Prior to joining ²ÝÁñÉçÇø, Ron held a range of management positions at Xilinx for automotive connectivity IP products as well as engineering development and management roles for companies including Oki Semiconductor, NEC, and Raytheon Corporation. Ron DiGiuseppe holds a bachelor's degree in Electrical Engineering from San Jose State University and a Certificate in Network Engineering from University of California.

Description: Flash memory IP is a complex block which contains both digital and analog parts, such as charge pumps and oscillators. Because of their relatively high operating frequency (can be above 100 MHz), they represent a huge cost in terms of simulation time, particularly for the erase operation. We propose a mixed mode simulation approach, based on XA-VCS to validate the Flash memory IP in a reasonable time with good level of precision. Flash bitcell modelling has been optimized, giving rise to huge runtime improvement.

Thomas Jouanneau

PHD, NVM Analog & Mixed Design, STMicroelectronics

Speaker: Thomas Jouanneau graduated from Grenoble INP in microelectronics engineering. After a PhD in process technology in the CEA-Leti, he was hired in STMicroelectronics Grenoble as digital back-end designer in 2012. He worked on digital SoC aimed for mobile phones or set-top-box. Since 2016, he moved to analog design for non-volatile memories in the Microcontroller & Digital Group. He is now focused on analog design, and full chip verification with Analog-Mixed-Signal simulation tools. He was recently appointed as Mixed-verification leader.