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Foundry-EDA Collaboration for Advanced Enablement and Readiness on Samsung 2nm and 1.4nm GAA Technology?
Pratima Eswar, Executive Director, R&D Engineering, ²ÝÁñÉçÇø
Ann-Woo Lee, Senior Manager, R&D Engineering, ²ÝÁñÉçÇø

Samsung Foundry (SF)'s new 2nm and 1.4nm GAA technology with back-side power delivery network methodology helps to overcome the performance limitations while improving power efficiency. Designers can now leverage new techniques including power routing and cell height variation to help meet aggressive performance, power and area targets. The beauty of SF's new 2nm and 1.4nm is to modulate and merge the gate width of the nanosheet, a Multi-Bridge-Channel FET (MBCFETTM), to further optimize and tune performance and power. To maximize PPA gains in 2nm and 1.4nm, SF and ²ÝÁñÉçÇø have been engaging in a DTCO (Design Technology Co-Optimization) collaboration and have co-developed key enablement features and methodologies. This presentation highlights the SF and ²ÝÁñÉçÇø collaboration results in 2nm and 1.4nm GAA technology, including back-side PDN and new features, early PPA effort with variable libraries, AI-driven reference flows and more.

²ÝÁñÉçÇø and Samsung Collaboration: PPA Boost Up for Advanced Node Designs
Chun-Soo Kim, Architect, R&D Engineering, ²ÝÁñÉçÇø

Cutting-edge technology is being used to optimize performance and reduce risk in submicron processes. In this session, ²ÝÁñÉçÇø will introduce its innovative design methodologies , like LLE-aware design methodology, augmented library enablement, and Half Row Offset(HRO) Flow architecture. Join us to learn how these technologies can reduce conservatism in conventional cell-characterization, mitigate this risk without recharacterization, and achieve impressive gains in Fmax and TNS reduction.

Robust Die-to-Die Connectivity with UCIe IP on Samsung Processes
Madhumita Sanyal, Sr. Technical Product Manager, ²ÝÁñÉçÇø

The UCIe standard has opened new opportunities in chiplet interoperability and multi-die innovations. It is established as the de facto standard for die-to-die connectivity, offering high-bandwidth, low-power and low-latency. By using UCIe IP on Samsung processes, companies can leverage the benefits of the standard and advance their multi-die design for high-performance computing, mobile, and automotive applications. This presentation provides an overview of the market landscape for die-to-die connectivity, details the ²ÝÁñÉçÇø and Samsung collaboration in developing IP for Samsung SF5, SF4, and SF2 processes, and showcases the UCIe IP on SF5 process silicon results. It also explains how companies can integrate this high-quality IP, which operates at 32G and supports advanced and standard package technologies, into chips using the Samsung process technologies.?

In-Field SLM & Test Solution ?for Highly Reliable Applications?
Yervant Zorian, Chief Technologist and Fellow,  Hardware Analytics and Test, ²ÝÁñÉçÇø

Recent advances in HPC engines in data centers, automotive SOCs, and AI accelerators have led to an explosion in the adoption of emerging technology nodes and 3DIC/chiplet packages. We will discuss the Silent Data Corruption (SDC) challenges for these emerging SOCs in the field, and optimizing the SoC health using prognostics, test and analytic solutions, utilized for managing silicon lifecycle (SLM) for improved quality and compliance to Reliability Availability Serviceability (RAS) requirements across application domains.