Cloud native EDA tools & pre-optimized hardware platforms
Welcome to the latest issue of the ASIP eUpdate Newsletter, our bi-annual publication to keep you informed on topics related to application-specific instruction-set processor (ASIP) design. ASIPs are a proven solution for domain-specific/application-optimized processors, and often serve as a more flexible yet equally efficient alternative to fixed RTL implementations, often referred to as programmable accelerators.
ASIPs come with an architecture and instruction set tuned for a specific application domain. They rely on techniques similar to those used in the design of hardware accelerators to reach high performance and low power: heavy use of parallelism and specialized datapath elements. Yet ASIPs retain software programmability within their application domain, resulting in C/C++ programmable processors and accelerators with the lowest power possible.
The March release of ASIP Designer? (2016.03) is available, and the September release (2016.09) is already on the horizon. The following highlights some new features.
The LLVM compiler infrastructure offers broad language support, including C and C++, and a large number of processor independent optimizations. To exploit these benefits, we developed a new compiler front-end based on the LLVM infrastructure, to be combined with the retargetable compiler backend of ASIP Designer. We extended the LLVM release in several ways, to support the full architectural freedom offered by ASIP Designer. These extensions include:
ASIP Designer comes with extensive C and C++ library support providing both a full-featured stack as well as a lightweight stack. The lightweight stack is tailored to the needs of embedded designs and results in significant savings on both cycle-count and instruction words.
ASIP Designer applies a single-source model approach using nML. All aspects of an ASIP are derived from one single nML model, so there is no need to keep multiple models in sync. This is also true for the two variants of an instruction-set simulator (ISS), which might be either cycle-accurate (CA) or instruction-accurate (IA). Both simulators are generated from the same nML model.
The example model library has been extended with a new model featuring the RISC-V instruction-set architecture. As with all other example models, the new model is provided in nML source code and can serve as the starting point for application-specific extensions and modifications. With ASIP Designer users can generate both synthesizable RTL, including JTAG debug logic, and a fully featured software development kit (SDK) including a C/C++ compiler, cycle-accurate and instruction-accurate instruction-set simulators, assembler / disassembler, and debugger.
There are many more enhancements that came with the 2016.03 release. For more features and additional details about the topics listed above, please refer to the ASIP Designer release notes, send a note to asipsupport@synopsys.com, or contact your local 草榴社区 representative. We will be happy to arrange for a specific update presentation. Also be sure to check out the updated and extended ASIP Designer data sheet, to get an overview of the features and capabilities of ASIP Designer.
Register now to download the datasheet: ASIP Designer: Design Tool for Application-Specific Instruction Set Processors
With the previous newsletter (December 2015) we gave an overview of the example models available with ASIP Designer. Designers can choose from this extensive library of example ASIP models, which are provided as nML source code. These models are an excellent reference to learn how to model certain processor functionalities in nML, to explain how the compiler can take advantage of the architectural specialization, and how to leverage the generated SDK. In combination with ASIP Designer, these models can be used as a starting point for architectural exploration, and customer-specific production designs. Starting with the current newsletter, we will drill one level deeper, giving an overview of specific example models. In this newsletter, we start with Tvec.
Tvec is an entire family of example models, all featuring the concept of single-instruction, multiple-data (SIMD). SIMD is an extremely efficient way to add parallelism with very little control. Its concept is widely applicable to many different application domains, including wireless, video and image processing – basically everywhere where an algorithm is most naturally described as a vector (therefore the name, Tvec). While the SIMD concept is fairly generic, different application domains require different implementations of SIMD – indeed leading to application-specific processors.
The list of features supported by Tvec is too long to list here, however the following is a subset of the basic and “special” features that are supported:
All Tvec examples come with a fully featured SDK, including a C/C++compiler that utilizes the specialized vector capabilities, a cycle-accurate and instruction-accurate simulator, and a graphical debugging environment.
For more details on these example models, or information on Tvec or any other example model, send a note to asipsupport@synopsys.com, or contact your local 草榴社区 representative.
Register to read our latest white paper: Software Development Kits (SDKs) for Proprietary Processors – Why They Matter, What It Takes to Develop Them
Teams designing in-house processors often find that they have limited time and expertise to create, deploy, maintain and support an SDK for their processor. Starting from a requirement specification for modern SDKs, this white paper describes how a tool-based approach using ASIP Designer can significantly enhance productivity. This is even true for existing processors that lack a sufficient SDK. By modeling the legacy processor in nML and using ASIP Designer, the time and effort needed to create the SDK can be significantly reduced, and 草榴社区’ deployment and support infrastructure can be leveraged.
Also register to download the following whitepapers: