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ASIPs have established themselves as an implementation option next to standard processor IP and fixed-function RTL. They combine hardware specialization with flexibility through software programmability.? This talk will provide an introduction into ²ÝÁñÉçÇø' ASIP Designer tool-suite, targeted markets, and how ²ÝÁñÉçÇø collaborates with university partners in this domain.

Our project aims to develop an AI-powered hearing aid system-on-chip (SoC) by integrating the application-specific instruction-set processor (ASIP) and dedicated accelerators. The SoC implements voice activity detection, speech enhancement, feedback cancellation, directional detection, and noise reduction to enhance speech clarity and reduce background noise. We have implemented the digital signal processing (DSP)-based functions, including speech enhancement, noise reduction, echo cancellation, and dynamic range compression through the ASIP Designer. Functional verification and time complexity analysis have been conducted and it is essential to ensure that the system's latency meets the requirements of the hearing aid devices. Neural network (NN)-based algorithms for speech enhancement and voice activity detection have been implemented. Dedicated accelerators will be included for performing compute-intensive operations. In the proposed system architecture, coordinate rotation digital computer (CORDIC) and fast Fourier Transform (FFT) engines will be deployed for DSP-based algorithms. Multiply-accumulate (MAC) computing units will be included for accelerating NN-based algorithms. Custom instructions will also be added to improve the performance with less cycle counts. The ASIP Designer enables to explore feasible architectures efficiently for a high-performance, power-efficient SoC for intelligent hearing aids.

Deep neural networks quickly evolve. The transformer model has recently been widely used in natural language processing, computer vision, and other application domains. Unlike the traditional convolutional neural networks, the transformer models include multiple mathematical operators such as the Softmax, the Sigmoid, and the Root Mean Square (RMS) normalization. Conventionally, the CPU processor transforms these sophisticated transcendental math functions into multiple simple instructions and slowly executes these mathematical operations. However, these mathematical operations in the transformer model are becoming a new performance bottleneck when specialized execution units fully accelerate the compute-intensive convolution and matrix multiplication. Consequently, we aim to reduce the model inference latency of edge transformer models such as the MobileViT model through the performance optimization of mathematical operations used by the transformer model. Unlike the traditional CPU Processor, our project designs create several specialized instructions, such as exponential and reciprocal functions used by the transformer model. We also added the SIMD execution to accelerate the convolutional and full-connected operators. In addition, we deployed TensorFlow Lite for Micro (TFLM) onto the ASIP designer to simplify the evaluation of the transformer model with the hardware beneath. Finally, our proposed RISC-V processor achieves a 1.62X speedup and reduces the 39.35% instruction count of the MobileViT model over the baseline. Based on the experience learned in this project, we also host an ASIP designer contest to create better RISC-V processor architecture for TinyML applications and an ASIP designer tutorial workshop in collaboration with ²ÝÁñÉçÇø engineers in Europe, mainland China, and Taiwan. This collaboration with ²ÝÁñÉçÇø engineers encourages more students in Taiwan to use the ASIP designer tool to design low-power and high-performance processor architecture.

Sphere decoding (SD), a key enabler for next generation wireless systems, demands not only implementation efficiency but also algorithm flexibility. A novel application-specific instruction set processor (ASIP), FlexSD, is proposed to support a variety of SD algorithms with high efficiency under varying channel conditions. To maximize the efficiency of FlexSD, the instruction set is designed on the basis of coarse-grained operations common to the target SD algorithms of interest. In addition, several instruction set architecture (ISA) options such as instruction level parallelism (ILP) and hardware resource scheduling are proposed. Given the ISA, the design automation tool from ²ÝÁñÉçÇø, the ASIP Designer, is utilized to generate the register transfer level models together with the compiler tool chains. The impact of each ISA option on the performance and the complexity of FlexSD is evaluated in a 28-nm CMOS technology. Logic synthesis results show that FlexSD accomplishes an area efficiency improvement of 2.35x through ISA optimization. Additionally, it is shown that the proposed FlexSD improves the power efficiency by 40% over the ASIC counterpart in certain channel conditions.

Brain-inspired Hyperdimensional Computing (HDC) presents a groundbreaking alternative to traditional machine learning algorithms. Unlike classical neural networks, HDC operates on high-dimensional vectors, where each vector is independent¡ªmaking it particularly well-suited for integration with RISC-V architectures. In this talk, I will present our development of a customized RISC-V processor, designed using the ²ÝÁñÉçÇø ASIP Designer tool. This processor features several specialized instructions tailored specifically for HDC, enabling it to efficiently handle both training and inference tasks. By synthesizing the processor's RTL code, we conducted a detailed evaluation of its area overhead and demonstrated gains in energy efficiency using cycle-accurate simulations. The processor is implemented using the 22nm GlobalFoundries technology, underscoring its practicality in commercial technologies. In the second part of the talk, I will showcase the ASIP Hackathon we organized at TU Munich, which provided hands-on experience with the ASIP Designer tool. Over 20 students, working in teams, optimized code for quantum computing using innovative approaches that leveraged ASIP¡¯s powerful features. This event not only highlighted the accessibility and flexibility of ASIP Designer but also inspired a new generation of engineers to explore custom processor design and chip design.

In this session we will present a case study on the design and implementation of an ASIP aimed at accelerating Swish and RMSNorm, these two algorithms are well-known and widely used in the AI/NN domain. Starting from functional and architectural requirements, we shall clarify the reasoning behind design designs and how ASIP Designer tool helped with creating an efficient processor architecture and optimal C-language applications code containing custom data types.

Currently, ensuring privacy and data protection has become a paramount concern, particularly in constrained environments. Ascon, a family of algorithms designed to be lightweight and easy to implement, was introduced as a standard to provide security and efficiency across a variety of applications. This work focuses on implementing an Application-Specific Integrated Processor (ASIP) specialized for Ascon, starting from one of the many processors available through ²ÝÁñÉçÇø¡¯ ASIP Designer tool. By leveraging the profiling capabilities of the tool, we identified bottlenecks in execution and resolved them by extending the RISC-V instruction set. As a result, the optimized processor computes the Ascon algorithm up to ten times faster than the baseline, outperforming other implementations by a factor of five. In addition, we explored other architectures to find the best balance between area usage and processing speed, ultimately achieving a speedup of x8.6 with only a 20% increase in area.

The continuous evolution towards smarter, software driven, and often AI-powered electronic systems is driving ASIP Designer customers to design ever more advanced ASIP architectures, with larger amounts of instruction-level and data parallelism, deeper instruction pipelines and more architectural specialization.  In turn, this is driving ²ÝÁñÉçÇø to continuously innovate and extend the scope of the ASIP Designer tool-suite.  In this presentation we will introduce several new tool innovations that empower architecture teams, RTL implementation teams and embedded software teams using ASIPs.  Specifically, we will zoom in on new capabilities for debugging and tracing, low-power optimizations at RTL level, and formal verification support in ASIP Designer.

ASIPs have established themselves as an implementation option next to standard processor IP and fixed-function RTL. They combine hardware specialization with flexibility through software programmability.? This talk will provide an introduction into ²ÝÁñÉçÇø' ASIP Designer tool-suite, targeted markets, and how ²ÝÁñÉçÇø collaborates with university partners in this domain.

Our project aims to develop an AI-powered hearing aid system-on-chip (SoC) by integrating the application-specific instruction-set processor (ASIP) and dedicated accelerators. The SoC implements voice activity detection, speech enhancement, feedback cancellation, directional detection, and noise reduction to enhance speech clarity and reduce background noise. We have implemented the digital signal processing (DSP)-based functions, including speech enhancement, noise reduction, echo cancellation, and dynamic range compression through the ASIP Designer. Functional verification and time complexity analysis have been conducted and it is essential to ensure that the system's latency meets the requirements of the hearing aid devices. Neural network (NN)-based algorithms for speech enhancement and voice activity detection have been implemented. Dedicated accelerators will be included for performing compute-intensive operations. In the proposed system architecture, coordinate rotation digital computer (CORDIC) and fast Fourier Transform (FFT) engines will be deployed for DSP-based algorithms. Multiply-accumulate (MAC) computing units will be included for accelerating NN-based algorithms. Custom instructions will also be added to improve the performance with less cycle counts. The ASIP Designer enables to explore feasible architectures efficiently for a high-performance, power-efficient SoC for intelligent hearing aids.

Deep neural networks quickly evolve. The transformer model has recently been widely used in natural language processing, computer vision, and other application domains. Unlike the traditional convolutional neural networks, the transformer models include multiple mathematical operators such as the Softmax, the Sigmoid, and the Root Mean Square (RMS) normalization. Conventionally, the CPU processor transforms these sophisticated transcendental math functions into multiple simple instructions and slowly executes these mathematical operations. However, these mathematical operations in the transformer model are becoming a new performance bottleneck when specialized execution units fully accelerate the compute-intensive convolution and matrix multiplication. Consequently, we aim to reduce the model inference latency of edge transformer models such as the MobileViT model through the performance optimization of mathematical operations used by the transformer model. Unlike the traditional CPU Processor, our project designs create several specialized instructions, such as exponential and reciprocal functions used by the transformer model. We also added the SIMD execution to accelerate the convolutional and full-connected operators. In addition, we deployed TensorFlow Lite for Micro (TFLM) onto the ASIP designer to simplify the evaluation of the transformer model with the hardware beneath. Finally, our proposed RISC-V processor achieves a 1.62X speedup and reduces the 39.35% instruction count of the MobileViT model over the baseline. Based on the experience learned in this project, we also host an ASIP designer contest to create better RISC-V processor architecture for TinyML applications and an ASIP designer tutorial workshop in collaboration with ²ÝÁñÉçÇø engineers in Europe, mainland China, and Taiwan. This collaboration with ²ÝÁñÉçÇø engineers encourages more students in Taiwan to use the ASIP designer tool to design low-power and high-performance processor architecture.

Sphere decoding (SD), a key enabler for next generation wireless systems, demands not only implementation efficiency but also algorithm flexibility. A novel application-specific instruction set processor (ASIP), FlexSD, is proposed to support a variety of SD algorithms with high efficiency under varying channel conditions. To maximize the efficiency of FlexSD, the instruction set is designed on the basis of coarse-grained operations common to the target SD algorithms of interest. In addition, several instruction set architecture (ISA) options such as instruction level parallelism (ILP) and hardware resource scheduling are proposed. Given the ISA, the design automation tool from ²ÝÁñÉçÇø, the ASIP Designer, is utilized to generate the register transfer level models together with the compiler tool chains. The impact of each ISA option on the performance and the complexity of FlexSD is evaluated in a 28-nm CMOS technology. Logic synthesis results show that FlexSD accomplishes an area efficiency improvement of 2.35x through ISA optimization. Additionally, it is shown that the proposed FlexSD improves the power efficiency by 40% over the ASIC counterpart in certain channel conditions.

Brain-inspired Hyperdimensional Computing (HDC) presents a groundbreaking alternative to traditional machine learning algorithms. Unlike classical neural networks, HDC operates on high-dimensional vectors, where each vector is independent¡ªmaking it particularly well-suited for integration with RISC-V architectures. In this talk, I will present our development of a customized RISC-V processor, designed using the ²ÝÁñÉçÇø ASIP Designer tool. This processor features several specialized instructions tailored specifically for HDC, enabling it to efficiently handle both training and inference tasks. By synthesizing the processor's RTL code, we conducted a detailed evaluation of its area overhead and demonstrated gains in energy efficiency using cycle-accurate simulations. The processor is implemented using the 22nm GlobalFoundries technology, underscoring its practicality in commercial technologies. In the second part of the talk, I will showcase the ASIP Hackathon we organized at TU Munich, which provided hands-on experience with the ASIP Designer tool. Over 20 students, working in teams, optimized code for quantum computing using innovative approaches that leveraged ASIP¡¯s powerful features. This event not only highlighted the accessibility and flexibility of ASIP Designer but also inspired a new generation of engineers to explore custom processor design and chip design.

In this session we will present a case study on the design and implementation of an ASIP aimed at accelerating Swish and RMSNorm, these two algorithms are well-known and widely used in the AI/NN domain. Starting from functional and architectural requirements, we shall clarify the reasoning behind design designs and how ASIP Designer tool helped with creating an efficient processor architecture and optimal C-language applications code containing custom data types.

Currently, ensuring privacy and data protection has become a paramount concern, particularly in constrained environments. Ascon, a family of algorithms designed to be lightweight and easy to implement, was introduced as a standard to provide security and efficiency across a variety of applications. This work focuses on implementing an Application-Specific Integrated Processor (ASIP) specialized for Ascon, starting from one of the many processors available through ²ÝÁñÉçÇø¡¯ ASIP Designer tool. By leveraging the profiling capabilities of the tool, we identified bottlenecks in execution and resolved them by extending the RISC-V instruction set. As a result, the optimized processor computes the Ascon algorithm up to ten times faster than the baseline, outperforming other implementations by a factor of five. In addition, we explored other architectures to find the best balance between area usage and processing speed, ultimately achieving a speedup of x8.6 with only a 20% increase in area.

The continuous evolution towards smarter, software driven, and often AI-powered electronic systems is driving ASIP Designer customers to design ever more advanced ASIP architectures, with larger amounts of instruction-level and data parallelism, deeper instruction pipelines and more architectural specialization.? In turn, this is driving ²ÝÁñÉçÇø to continuously innovate and extend the scope of the ASIP Designer tool-suite. ?In this presentation we will introduce several new tool innovations that empower architecture teams, RTL implementation teams and embedded software teams using ASIPs. ?Specifically, we will zoom in on new capabilities for debugging and tracing, low-power optimizations at RTL level, and formal verification support in ASIP Designer.