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²ÝÁñÉçÇø¡¯ ASIP Designer? is the market-leading tool suite for automating and accelerating the design of highly-efficient application-specific instruction-set processors. This includes both the design of the hardware as well as the corresponding software development kit (SDK), all being generated from a single description of the processor.

This online training is divided in two blocks that can be digested independently. 

The first block provides a deep dive into the concepts, languages and files that are used to capture a processor design in ASIP Designer. The processor model of the target processor is described in the special-purpose language "nML", which is a register transfer level language that models the processor at the abstraction level of a programmer¡¯s manual. Complementarily, the functional behavior of instructions and program independent modules such as the processor control unit and I/O interfaces are modeled in a C-style language called ¡°PDG¡±. Finally, a compiler processor header file describes the mapping of C data types and operators to the instruction set architecture. This first block of the training comprises 6 modules:

1.  ASIP Designer Introduction

2.  Primitives Declaration and Definition

3.  The nML Processor Description Language

4.  PDG Modules

5.  The compiler Processor Header file

6.  Example Processor Models

The second block of the training describes the different aspects of the ASIP Designer tool itself, including the IDE, the compiler, the simulator, the RTL generator, the verification concept, and On-Chip-Debugging.

This second block comprises 6 modules:

7.  The Chess Development Environment 

8.  Chess Compiler Usage

9.  The Checkers ISS Generator

10. The Go RTL Generator

11. Processor Verification

12. On-Chip Debugging

Target audience: engineers who intend to develop an in-house processor, including a fully featured software development kit

Goal of the training: teach how to create a processor model for ASIP Designer and how to use the ASIP Designer tool set

Prerequisites: basic knowledge of processor architectures, the C programming language, and RTL design