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ASIP eUpdate September 2024
ASIP Designer
草榴社区’ solution to efficiently design and implement your own application-specific instruction-set processor (ASIP) when you can’t find suitable processor IP, or when hardware implementations require more flexibility.
This bi-annual newsletter provides you with easy access to ASIP-related resources. This issue includes the following topics:
Technology Feature I: Lauterbach TRACE32? Interoperability
Overview
With ASIP Designer? V-2024.06, we introduce interoperability with Lauterbach’s TRACE32? debug and trace tools. TRACE32 support includes debugging the ASIP cores on-chip as well as using the generated ASIP instruction-set simulator.
草榴社区 and Lauterbach engineering teams worked closely together to ensure interoperability between ASIP Designer and TRACE32. Lauterbach extended support for their TRACE32? debug and trace tools to ASIPs created with the V-2024.06 release of 草榴社区 ASIP Designer. To achieve this, ASIP Designer generates a TRACE32 API for both the cycle-accurate simulator and the debug client. As a result, TRACE32 and the API can support the wide architectural scope of ASIP Designer, including specialized scalar processors, very-long instruction word (VLIW) and wide vector processors.
Figure 1 shows a screenshot of a typical ASIP debugging scenario using TRACE32. The layout simultaneously displays the source code and assembly view, register view, memory view, variable information, breakpoints, and the stack and locals.
Figure 1: ASIP debugging in TRACE32? environment
For more information, please click on this link to read the latest from Lauterbach.
Technology Feature II: Architectural Clock Gating of Hierarchical Modules
To enhance low-power optimization at various levels of granularity, ASIP Designer V-2024.06 now supports architectural clock gating for hierarchical modules.
The existing hierarchy option of the Go tool (ASIP Designer’s RTL generator) allows users to group a collection of generated lower-level RTL modules into a named, user-defined hierarchical module. With the new Go option gated_clock_for_hierarchy, users can now specify a gated clock for this hierarchy. Go automatically infers the clock-enable signal from the decoder that controls the functional units within the hierarchy and instantiates a clock-gating cell. An example of the generated RTL structure is shown in Figure 2.
Figure 2: Architectural Clock Gating Example
The large light purple box represents a user-defined hierarchical module named gated_hry, which we assume was defined using the Go option hierarchy. With the new Go option gated_clock_for_hierachy, a separate gated clock gclk is defined for this hierarchical module. This clock is driven by the clock gating cell gclk_cg_cell, which is automatically generated by Go. The clock-enable signal gclk_clken is automatically inferred by Go from the decoder that drives the enablings of the functional units within the hierarchical module.
If the hierarchy includes IO interfaces or multi-cycle functional units (MCFUs), the user must specify the extra enablings driving the clock-gating cell, using a separate Go option. In the example, this is the div_busy signal coming out of the multi-cycle divider unit div_fu. Additional Go options allow users to configure the implementation style of the clock-gating cell, such as choosing between AND-based or OR-based logic, and to determine whether the clock-enable signals should be registered.
Next to the instantiation of the gated clock infrastructure, the Go option gated_clock_for_hierarchy automatically generates a report summarizing the inferred enable signals for all clock enablings, as well as the active cycles of the gated clock for each listed hierarchy.
What’s New: ASIP Designer V-2024.06 Release
Since the last edition of this newsletter, we have launched a new feature release for ASIP Designer in June 2024, offering various enhancements and extensions. Below is a categorized summary of these updates (customers can refer to the official Release Notes for a comprehensive list of details).
Click on each tab for additional information about that new feature
Example Processor Models
The following updates have been made to the library of example processor models:
- An example test suite with unit tests for primitive operations has been added to the “Tmicro” model
- The C++ light-weight library stack has been updated
Processor Modeling
- Support for enumeration types has been added to the PDG language. Thanks to a common syntax, these enumeration types can be shared across both PDG and nML.
C/C++ Compiler
- Store intrinsics with a boolean predicate argument are evaluated to optimize away small if-statements that contain memory store accesses.
- The new node-based list scheduling algorithm provides better optimization for code size.
- Enhancements to the LLVM compilation flow were implemented:
- A new manual documents the Chess LLVM IR interface, describing the LLVM IR input accepted by the LLVM front end of the CHESS compiler, as an alternative to C/C++ source files. This format follows the LLVM IR as used by the LLVM project, enhanced with additional CHESS extensions and specifics to support the full ASIP architectural scope.
- The LLVM front-end has been updated to LLVM version 18.0.
- The libc++ Lite library has been updated to LLVM version 16.
ChessDE GUI, Instruction-Set Simulation and Debugging
- Interoperability with Lauterbach TRACE32? tools. See “Technology Feature I: Lauterbach TRACE32 interoperability” above.
- The language server support, which has been introduced to the ChessDE editor in Release U-2022.12, has been further enhanced and extended with additional functionality.
- Editor extensions: comment/uncomment/backslashify region.
- GDB support has been updated to version 13.2.
RTL Generation, Verification, and Synthesis Support
- Support for architectural clock gating of hierarchical modules. See “Technology Feature II: Architectural Clock Gating of Hierarchical Modules” above.
- Formal ISA Verification, which has been introduced in Release V-2023.12 as part of the Advanced Verification Add-On product, has been extended to cover a broader architectural scope.
Additional Resources
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