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By Kenneth Larsen, Director of Product Management, 草榴社区, and S.Z. Chang, VP and CTO, Powerchip Semiconductor Manufacturing Corporation
3DIC design is becoming a big deal. The increasing demands of AI-enabled applications in today's market and the slowing pace of Moore's law have necessitated chip designers to look for other types of chip architecture that will help support the advancements that consumers and leading service providers have come to expect. Instead of simply connecting multiple silicon dies next to each other, 3DIC design offers orders of magnitude better performance, power benefits, and a smaller footprint via vertical stacking of silicon wafers or dies.
That is why 草榴社区 and Powerchip Semiconductor Manufacturing Corporation (PSMC) have worked together to offer a new wafer-on-wafer (WoW) and Chip-on-Wafer (CoW) solution, a specific kind of 3DIC design, by utilizing 草榴社区 3DIC Compiler Platform and PSMC's advanced process technologies to create a new joint solution that makes it possible to create circuits that stack and bond DRAM memory directly on top of a silicon chip at a reduced effort.
Figure 1: Chip bump, TSV, and hybrid bond visualization of 3D stacked dies in 草榴社区 3DIC Compiler.
“The sheer complexity of 3DIC design, especially stacking memory and logic dies, requires the expertise of many players in the semiconductor ecosystem”, said Chang. “We are excited to closely collaborate with 草榴社区 to offer this cutting-edge solution that will reduce the time designers take to combine multiple semiconductor wafers into one 3D design by one to two months, as well as reduce the many costly iterations currently required for stacking two dies.”
Read on to discover more about WoW, hybrid bonding, and its major benefits, why DRAM-logic stacking benefits innovative AI applications, and how this new 草榴社区-PSMC offering delivers improved engineering productivity time-to-volume advantages.
What is WoW and CoW Hybrid Bonding?
A type of 3D design, wafer-on-wafer hybrid bonding stacks electrically connect different wafers to create a single integrated device. Each wafer has tiny copper pads that are permanently bonded together, forming tens of thousands to millions of circuit interconnects. The related chip-on-wafer hybrid bonding may be a more practical approach for designs with different chip sizes. With WoW and CoW 3D stacking, hybrid bonding shortens signal transmission distance at no wasted power and provides more interconnect and bandwidth density than any other 3D integration scheme. The technology may be scaled to sub-micron interconnects to enable widespread disaggregation and chiplet architecture innovation.
PSMC development efforts target wafer-to-wafer stacking with pitches below 3um, which is enabled with the existing Si supply chain. Moreover, PSMC's collaboration with 草榴社区 has successfully demonstrated wafer-level multi-stacking structure by applying robust Cu-to-Cu bonding combined with through-Si-via (TSV) process.
Figure 2: Fine pitch interconnect scaling, L. Jiang et al., ECTC 2022
However, compared with other approaches, hybrid bonding is much more intricate, and with that complexity comes cost. But for advanced applications like AI training engines, this cost is well worth it since it provides significant memory bandwidth density and low latency. Using hybrid bonding to stack memory on logic provides the performance and latency necessary for AI and many additional improvements over traditional 2D and even 2.5D designs.
Figure 3: Hybrid bonding process flow. Albert Lan et al, 17th International Conference on device packaging 2021
The Challenges of Stacking DRAM on Logic
Chip designers have long been strategizing how to best stack processor and memory. There are many factors to consider — selecting heterogenous or homogeneous integration, how to best deliver power up through the die stack, thermal management, in-stack PVT sensors, stress-induced performance and reliability issues, and more.
Figure 4: DRAM stacked on processor die, thermal visualization in 草榴社区 3DIC Compiler.
“These factors get even more complicated when you are stacking dynamic random-access memory (DRAM) rather than static random-access memory (SRAM) because DRAM’s retention of data is sensitive to temperature”, said Larsen. “It demonstrates that the operating temperature of processor and DRAM in a 3D stacked structure could reach 120°C/110°C, compared to 55°C in a 2D DRAM structure.”
Higher temperatures will cause DRAM to lose data faster as a result of charge leakage. Hence, more self-refresh sessions are required in a given period to keep the data in a healthy state. Chip designers needs to explore how temperature impacts the overall system performance.
Figure 5: For DRAM, retention time is sensitive to temperature.
When DRAM is stacked on top of logic, the heat produced by the compute logic die at the base goes up through the memory, creating the need to design for thermal and for heat escape.
Finally, different suppliers or design groups are responsible for memory and logic design, which can result in disjointed flows when stacking the two because there are no common interfaces to discuss between the teams or exchange designs. Additionally, the geometries and processes to shrink them are different; for example, one is 100% GDS and the other is 90% shrink GDS. These challenges require an innovative EDA solution to allow designers to get from the designing phase to manufacturing.
Efficient Multi-Die System Integration
PSMC's collaboration with 草榴社区 for this new solution mostly relies on the 草榴社区 3DIC Compiler platform, a complete, end-to-end solution for efficient 3D multi-die system integration. Built on the common fusion data-model infrastructure of the 草榴社区 Digital Design Family, 3DIC Compiler merges numerous transformative, multi-die design capabilities to offer a complete 3D architecture-to-signoff platform. This solution includes immersive 2D and 3D visualization, cross-hierarchy exploration and planning, design and implementation, DFx, system-level validation, and signoff analysis.
Figure 6: Interposer with DRAM processor.
The system's full connectivity model can be modeled within 3DIC Compiler or imported via standard netlists and various text formats. 3DIC Compiler offers capabilities to create connections between the bottom and top dies, which saves chip designers up to two months compared to manual methods. There are multiple steps and checks required to optimize a chip through the concept, design, implementation, and manufacturing phases.
One such step is 3D system connectivity check that verifies electrical, logical, and physical connectivity between semiconductor dies, die stacks, interposers, embedded bridges, and package substrate. Electrical connections from a logical die pad on a die to primary IO, the physical connection between bond and bump, can be checked in-design, and violations such as incomplete or shorted nets can be pinpointed. The same can be said for 3D design rule checking, die mirroring stacking, bonding coordination, and power and DFT checking.
Figure 7: Thermal map of TSVs, visualization in 草榴社区 3DIC Compiler.
With 3DIC Compiler, 草榴社区 software checks that the signals and power go through the bottom die to get to the top die via TSVs correctly. It can also do thermal simulations necessary to model the interactions between the two dies consume power and subsequently generate heat. This heat that sits between two dies needs to be dispersed, and 3DIC Compiler can facilitate different methods that do just that.
Figure 8: Wafer-on-wafer solution. Image courtesy of Powerchip.
Ultimately, customers using PSMC and 草榴社区’ new 3D wafer-on-wafer and chip-on-wafer solution can rest assured that the entire process from tape-out is aided by the certified 草榴社区 Digital Design Family, which 3DIC Compiler is built on. This new solution provides high bandwidth between the memory and logic dies, enhancing the AI inference performance and speed.
The overarching requirements for memory bandwidth, IO, and compute power will only grow with time as we integrate AI technology into more aspects of our daily lives and expect it to become even more sophisticated. Advanced packaging is the answer that today and tomorrow’s chip designers will look to as Moore’s law slows down. Products like 3DIC Compiler are helping designers meet these emerging application demands quickly and efficiently to advance the field of AI and beyond.