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Welcome to the wonderfully complex and rich world of multi-die systems. Breaking free from the monolithic SoC mold, multi-die systems integrate heterogeneous dies into a single package. This relatively new architecture is steadily transforming the semiconductor industry by allowing chip designers to reach new heights of functionality with higher compute power and the ability to reuse proven dies, enabling more powerful systems in phones, computers, and even self-driving cars. However, with rapid advancement comes challenges, many of which were discussed at last month¡¯s Accelerating Mainstream Adoption of Multi-Die Systems panel discussion, hosted by ²ÝÁñÉçÇø.

This virtual event brought together Murat Becer, vice president of research and development at Ansys, Inc.; Michael Schaffert, senior vice president at Bosch; Cheolmin Park, corporate vice president at Samsung; Lalitha Immaneni, vice president of architecture, design, and technology solutions at Intel; and Shekhar Kapoor, senior director of product line management at ²ÝÁñÉçÇø. The panel was moderated by Marco Chiapetta, co-founder and principal analyst at HotTech Vision and Analysis, and touched on the current state of multi-die system design, its applications, and the industry¡¯s expectations for multi-die system adoption.

Read on for highlights from the panel and insights into why industry leaders believe collaboration is critical to accelerating the adoption of multi-die systems.

Expanding the Use of Multi-Die Systems

Multi-die systems have enabled chip designers to reduce both risk and time to market. For this reason, there¡¯s been a notable expansion in the past two to three years, which is a far cry from the sporadic use across the industry in the past. During the panel, Samsung¡¯s Park weighed in on key segments emerging in the multi-die system landscape.

¡°Adoption started mainly from high-performance computing (HPC),¡± said Park. ¡°Now, we have folks in the mobile and automotive units that are seriously thinking of bringing those multi-die systems into those application spaces. What it really means is that the portfolio of technology and adoption of technology is expanding very fast. As a manufacturer and enabler in the market, we are really happy to see the ecosystem of multi-die systems expanding.¡±

Ansys¡¯ Becer noted substantial growth in 3DIC design over the last year, forecasting even more growth in the future. He also touched on heterogeneous integration, a significant driver for adopting multi-die systems.

¡°The forecast for 3DIC is continuing to accelerate," said Becer. "In fact, we are seeing around a 3X increase in the number of 3DIC design starts this year versus last year, which means 3DIC is here to stay. One of the major benefits that influences further adoption is enabling heterogeneous integration. You can choose the best technology for each chiplet, meaning that you can bring in an analog, mixed-signal, or RF chiplet or you can use an older, more mature, or lower power node.¡±

²ÝÁñÉçÇø¡¯ Kapoor echoed the sentiment of rapid growth within multi-die systems use, noting that ²ÝÁñÉçÇø has seen a definitive increase in the usage of multi-die system designs, currently tracking over 100 multi-die system projects in the industry, spanning various package types and applications.

Addressing Challenges in Multi-Die Systems

Challenges with integrating multi-die systems range from packaging optimization to high temperatures. Intel¡¯s Immaneni and Ansys¡¯ Becer provided insight into both issues during the panel. 

¡°The burden of these multi-die systems lies much more in the co-design and architecture than the execution and building," said Immaneni. "You¡¯re bringing these IPs that are built on various process nodes, so you need to pick the right packaging technology. You also need to pick the right board technology." 

Beyond the industry¡¯s need to come together and create standards for optimizing multi-die systems, other factors such as thermal challenges need to be addressed. Ansys¡¯ Becer gave some insight into the risks of thermal stress.

He explained: "Multiple dies in the system create thermal challenges, and high temperatures are creating structural challenges, with possible disconnects in bumps due to thermal stress. High-speed digital signals for die-to-die communication through interposer require much higher fidelity electromagnetic aware extraction for more accurate signal integrity analysis. So, there are a lot of multi-physics challenges that are in play."

Calling for Semiconductor Industry Collaboration

During the panel, all speakers expressed a commitment to collaboration across the industry. Immaneni touched on the need to develop reusable IP, while Becer echoed an exciting vision of industry partnerships.

¡°Building off-the-shelf, pre-validated IPs on various process notes is what the IP vendors are looking into,¡± Immaneni of Intel said. ¡°UCIe is a great start. It¡¯s a die-to-die connectivity interface that the industry came together to support.¡±

Becer also pointed to a strong partnership between Ansys and ²ÝÁñÉçÇø: ¡°We all know that EDA flows are all composed of best-in-class products from multiple vendors. It¡¯s not possible for one company to solve all the challenges. Partnerships are going to be key going forward, and I¡¯m very happy to say that Ansys and ²ÝÁñÉçÇø have been working along these lines and partnering in several key parts of the design cycle, really exemplifying the value of seamless workflows with market-leading products.¡±

As for the future of multi-die systems, ¡°there¡¯s a genuine rush from almost all corners of the industry to understand the multi-die system, what it is, and what it has to offer,¡± as ²ÝÁñÉçÇø¡¯ Kapoor put it. 

Multi-die systems¡¯ unprecedented functionality and their ability to hit precise performance targets create a large incentive for the industry to come together to address newfound challenges and complexity. With the rapid advancements in AI, mobile markets, and automotive technology, it¡¯s apparent that multi-die systems are here to stay.